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| MC68HC908AB32/d rev. 1.0 MC68HC908AB32 hcmos microcontroller unit technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola list of sections 3 technical data ?MC68HC908AB32 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . .29 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . .41 section 3. random-access memory (ram) . . . . . . . . . .57 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . .59 section 5. eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 section 6. configuration register (config) . . . . . . . . .85 section 7. central processor unit (cpu) . . . . . . . . . . . .89 section 8. system integration module (sim) . . . . . . . .109 section 9. clock generator module (cgm) . . . . . . . . . .131 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . .157 section 11. timer interface module a (tima) . . . . . . . .169 section 12. timer interface module b (timb) . . . . . . . .195 section 13. programmable interrupt timer (pit) . . . . .221 section 14. analog-to-digital converter (adc) . . . . . .229 section 15. serial communications interface module (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 section 16. serial peripheral interface module (spi) . .279 section 17. input/output (i/o) ports . . . . . . . . . . . . . . .311 section 18. external interrupt (irq) . . . . . . . . . . . . . . .339 section 19. keyboard interrupt module (kbi). . . . . . . .345 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections technical data MC68HC908AB32 ? rev. 1.0 4 list of sections motorola section 20. computer operating properly (cop) . . . .353 section 21. low-voltage inhibit (lvi) . . . . . . . . . . . . . .359 section 22. break module (brk) . . . . . . . . . . . . . . . . . .365 section 23. electrical specifications . . . . . . . . . . . . . . .373 section 24. mechanical specifications . . . . . . . . . . . . .387 section 25. ordering information . . . . . . . . . . . . . . . . .389 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 5 technical data ?MC68HC908AB32 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 34 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 35 1.6.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.7 analog ground pin (a vss /v refl ). . . . . . . . . . . . . . . . . . . . . 35 1.6.8 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . 36 1.6.9 analog supply pin (v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . 36 1.6.11 port a input/output (i/o) pins (pta7?ta0) . . . . . . . . . . . . 36 1.6.12 port b i/o pins (ptb7/atd7?tb0/atd0) . . . . . . . . . . . . . 36 1.6.13 port c i/o pins (ptc5?tc0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.14 port d i/o pins (ptd7?td0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.15 port e i/o pins (pte7/spsck?te0/txd) . . . . . . . . . . . . . 37 1.6.16 port f i/o pins (ptf7?tf0/tach2) . . . . . . . . . . . . . . . . . 37 1.6.17 port g i/o pins (ptg2/kbd2?tg0/kbd0) . . . . . . . . . . . . 37 1.6.18 port h i/o pins (pth1/kbd4?th0/kbd3). . . . . . . . . . . . . 37 1.7 i/o pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.8 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.9 clock source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 6 table of contents motorola section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.7 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . 63 4.8 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.1 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . 66 4.9 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.10 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 5. eeprom 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 7 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 eeprom timebase requirements . . . . . . . . . . . . . . . . . . . . . 72 5.7 eeprom security options. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.9 eeprom programming and erasing . . . . . . . . . . . . . . . . . . . . 73 5.9.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.9.2 eeprom erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11 eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.1 eeprom control register. . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.2 eeprom array configuration register . . . . . . . . . . . . . . . . 79 5.11.2.1 eeprom non-volatile register . . . . . . . . . . . . . . . . . . . 80 5.11.3 eeprom timebase divider register . . . . . . . . . . . . . . . . . 80 5.11.3.1 eeprom timebase divider non-volatile register . . . . . 82 section 6. configuration register (config) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 section 7. central processor unit (cpu) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 8 table of contents motorola 7.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 section 8. system integration module (sim) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 112 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . 113 8.3.3 clocks in stop and wait modes . . . . . . . . . . . . . . . . . . . . . 113 8.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . 114 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.2.2 computer operating properly (cop) reset . . . . . . . . . 116 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 117 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.5.1 sim counter during power-on reset. . . . . . . . . . . . . . . . . 118 8.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . 118 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 118 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 9 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 123 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 129 section 9. clock generator module (cgm) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.4.1 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4.2 phase-locked loop (pll) circuit . . . . . . . . . . . . . . . . . . . 135 9.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 136 9.4.2.3 manual and automatic pll bandwidth modes . . . . . . . 136 9.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 139 9.4.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.4 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 142 9.5.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . 142 9.5.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . 142 9.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 142 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 10 table of contents motorola 9.5.5 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 142 9.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 143 9.5.7 cgm base clock output (cgmout). . . . . . . . . . . . . . . . . 143 9.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 143 9.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 146 9.6.3 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . 148 9.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.9 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.10 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . 151 9.10.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . . 152 9.10.2 parametric influences on reaction time. . . . . . . . . . . . . . 153 9.10.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . 154 9.10.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . 155 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.6 extended security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 11 section 11. timer interface module a (tima) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . 176 11.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . 177 11.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 178 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 179 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.8 tima during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.9.1 tima clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.9.2 tima channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.10.1 tima status and control register . . . . . . . . . . . . . . . . . . . 184 11.10.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.10.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . 187 11.10.4 tima channel status and control registers . . . . . . . . . . . 188 11.10.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 12 table of contents motorola section 12. timer interface module b (timb) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . 202 12.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . 203 12.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 204 12.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 205 12.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.8 timb during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.9.1 timb clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.9.2 timb channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.10.1 timb status and control register . . . . . . . . . . . . . . . . . . . 210 12.10.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.10.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . 213 12.10.4 timb channel status and control registers . . . . . . . . . . . 214 12.10.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 218 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 13 section 13. programmable interrupt timer (pit) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4.1 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.6 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.7.1 pit status and control register. . . . . . . . . . . . . . . . . . . . . 225 13.7.2 pit counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.7.3 pit counter modulo registers . . . . . . . . . . . . . . . . . . . . . . 228 section 14. analog-to-digital converter (adc) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.7.1 adc analog power pin (v ddaref ). . . . . . . . . . . . . . . . . . . 234 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 14 table of contents motorola 14.7.2 adc analog ground pin (a vss /v refl ) . . . . . . . . . . . . . . . 234 14.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 234 14.7.4 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8.1 adc status and control register (adscr). . . . . . . . . . . . 235 14.8.2 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . 237 14.8.3 adc clock register (adclk) . . . . . . . . . . . . . . . . . . . . . . 237 section 15. serial communications interface module (sci) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.5 inversion of transmitted output. . . . . . . . . . . . . . . . . . . 249 15.5.2.6 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 249 15.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 15.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 15 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . 260 15.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 15.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 15.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 section 16. serial peripheral interface module (spi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.4 pin name conventions and i/o register addresses . . . . . . . 281 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 16.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 16.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 285 16.6.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . 286 16.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 288 16.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 289 16.7 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 16 table of contents motorola 16.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 301 16.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 301 16.13.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.5 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . . 306 16.14.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 section 17. input/output (i/o) ports 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 316 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 319 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 321 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 324 17.6.3 port d input pullup enable register (ptdpue). . . . . . . . . 325 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 17 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . 328 17.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.1 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.2 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . 330 17.8.3 port f input pullup enable register (ptfpue) . . . . . . . . . 332 17.9 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.1 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.2 data direction register g (ddrg) . . . . . . . . . . . . . . . . . . 333 17.10 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.1 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.2 data direction register h (ddrh). . . . . . . . . . . . . . . . . . . 335 section 18. external interrupt (irq) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 18.5 irq status and control register (iscr) . . . . . . . . . . . . . . . . 343 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 344 section 19. keyboard interrupt module (kbi) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 19.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 19.5.2 keyboard status and control register. . . . . . . . . . . . . . . . 349 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 18 table of contents motorola 19.5.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 351 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 352 section 20. computer operating properly (cop) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 356 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 358 section 21. low-voltage inhibit (lvi) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC908AB32 ? rev. 1.0 technical data motorola table of contents 19 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 21.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.5 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 section 22. break module (brk) 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4.1 flag protection during break interrupts . . . . . . . . . . . . . . . 368 22.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 368 22.4.3 pit, tima, and timb during break interrupts . . . . . . . . . . 368 22.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 368 22.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 22.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 22.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 22.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 22.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 369 22.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 372 section 23. electrical specifications 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data MC68HC908AB32 ? rev. 1.0 20 table of contents motorola 23.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 376 23.7 eeprom and memory characteristics . . . . . . . . . . . . . . . . . 377 23.8 5.0-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 378 23.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 23.11 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 23.12 clock generation module characteristics . . . . . . . . . . . . . . . 383 23.12.1 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 383 23.12.2 cgm component information . . . . . . . . . . . . . . . . . . . . . . 383 23.12.3 cgm acquisition/lock time information . . . . . . . . . . . . . . 384 23.13 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 385 section 24. mechanical specifications 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 388 section 25. ordering information 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola list of figures 21 technical data ?MC68HC908AB32 list of figures figure title page 1-1 MC68HC908AB32 block diagram . . . . . . . . . . . . . . . . . . . . . . 32 1-2 64-pin qfp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-3 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . . 45 4-1 flash control register (flcr) . . . . . . . . . . . . . . . . . . . . . . . 60 4-2 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 65 4-4 flash block protect start address . . . . . . . . . . . . . . . . . . . . . 66 4-3 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 66 5-1 eeprom i/o register summary . . . . . . . . . . . . . . . . . . . . . . . 70 5-2 eeprom control register (eecr) . . . . . . . . . . . . . . . . . . . . . 77 5-3 eeprom array configuration register (eeacr) . . . . . . . . . . 79 5-4 eeprom non-volatile register (eenvr) . . . . . . . . . . . . . . . . 80 5-5 eeprom divider register high (eedivh) . . . . . . . . . . . . . . . 81 5-6 eeprom divider register low (eedivl) . . . . . . . . . . . . . . . . 81 5-7 eeprom divider non-volatile register high(eedivhnvr) . . 82 5-8 eeprom divider non-volatile register low (eedivlnvr) . . 82 6-1 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 86 6-2 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . . 88 7-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 94 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data MC68HC908AB32 ? rev. 1.0 22 list of figures motorola figure title page 8-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8-3 cgm clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8-8 interrupt entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8-9 interrupt recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 121 8-12 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8-13 wait recovery from interrupt or break . . . . . . . . . . . . . . . . . . 125 8-14 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 125 8-15 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8-16 stop mode recovery from interrupt or break . . . . . . . . . . . . . 126 8-17 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . . 127 8-18 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 128 8-19 sim break flag control register (sbfcr) . . . . . . . . . . . . . . 129 9-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9-2 cgm i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . 134 9-3 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9-4 cgm i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . 144 9-5 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . . 144 9-7 pll bandwidth control register (pbwc) . . . . . . . . . . . . . . . 146 9-8 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . 148 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10-2 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10-5 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10-6 monitor mode entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11-1 tima block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures MC68HC908AB32 ? rev. 1.0 technical data motorola list of figures 23 figure title page 11-2 tima i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . 173 11-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . . . 177 11-4 tima status and control register (tasc) . . . . . . . . . . . . . . . 184 11-5 tima counter register high (tacnth). . . . . . . . . . . . . . . . . 186 11-6 tima counter register low (tacntl) . . . . . . . . . . . . . . . . . 187 11-7 tima counter modulo register high (tamodh). . . . . . . . . . 187 11-8 tima counter modulo register low (tamodl) . . . . . . . . . . 187 11-9 tima channel 0 status and control register (tasc0) . . . . . 188 11-10 tima channel 1 status and control register (tasc1) . . . . . 188 11-11 tima channel 2 status and control register (tasc2) . . . . . 189 11-12 tima channel 3 status and control register (tasc3) . . . . . 189 11-13. chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11-14 tima channel 0 register high (tach0h) . . . . . . . . . . . . . . . 192 11-15 tima channel 0 register low (tach0l). . . . . . . . . . . . . . . . 192 11-16 tima channel 1 register high (tach1h) . . . . . . . . . . . . . . . 193 11-17 tima channel 1 register low (tach1l). . . . . . . . . . . . . . . . 193 11-18 tima channel 2 register high (tach2h) . . . . . . . . . . . . . . . 193 11-19 tima channel 2 register low (tach2l). . . . . . . . . . . . . . . . 193 11-20 tima channel 3 register high (tach3h) . . . . . . . . . . . . . . . 194 11-21 tima channel 3 register low (tach3l). . . . . . . . . . . . . . . . 194 12-1 timb block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12-2 timb i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . 199 12-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . . . 203 12-4 timb status and control register (tbsc) . . . . . . . . . . . . . . . 210 12-5 timb counter register high (tbcnth). . . . . . . . . . . . . . . . . 212 12-6 timb counter register low (tbcntl) . . . . . . . . . . . . . . . . . 213 12-7 timb counter modulo register high (tbmodh). . . . . . . . . . 213 12-8 timb counter modulo register low (tbmodl) . . . . . . . . . . 213 12-9 timb channel 0 status and control register (tbsc0) . . . . . 214 12-10 timb channel 1 status and control register (tbsc1) . . . . . 214 12-11 timb channel 2 status and control register (tbsc2) . . . . . 215 12-12 timb channel 3 status and control register (tbsc3) . . . . . 215 12-13. chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12-14 timb channel 0 register high (tbch0h) . . . . . . . . . . . . . . . 218 12-15 timb channel 0 register low (tbch0l). . . . . . . . . . . . . . . . 218 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data MC68HC908AB32 ? rev. 1.0 24 list of figures motorola figure title page 12-16 timb channel 1 register high (tbch1h) . . . . . . . . . . . . . . . 219 12-17 timb channel 1 register low (tbch1l). . . . . . . . . . . . . . . . 219 12-18 timb channel 2 register high (tbch2h) . . . . . . . . . . . . . . . 219 12-19 timb channel 2 register low (tbch2l). . . . . . . . . . . . . . . . 219 12-20 timb channel 3 register high (tbch3h) . . . . . . . . . . . . . . . 220 12-21 timb channel 3 register low (tbch3l). . . . . . . . . . . . . . . . 220 13-1 pit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13-2 pit i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13-3 pit status and control register (psc) . . . . . . . . . . . . . . . . . 225 13-4 pit counter register high (pcnth) . . . . . . . . . . . . . . . . . . . 227 13-5 pit counter register low (pcntl) . . . . . . . . . . . . . . . . . . . . 228 13-6 pit counter modulo register high (pmodh) . . . . . . . . . . . . 228 13-7 pit counter modulo register low (pmodl) . . . . . . . . . . . . . 228 14-1 adc register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14-3 adc status and control register (adscr) . . . . . . . . . . . . . . 235 14-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 14-5 adc clock register (adclk) . . . . . . . . . . . . . . . . . . . . . . . . 237 15-1 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 243 15-2 sci i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 15-3 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15-4 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 15-5 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 251 15-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15-7 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 15-8 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 15-9 sci control register 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . . 262 15-10 sci control register 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . . 265 15-11 sci control register 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . . 267 15-12 sci status register 1 (scs1) . . . . . . . . . . . . . . . . . . . . . . . . 269 15-13 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15-14 sci status register 2 (scs2) . . . . . . . . . . . . . . . . . . . . . . . . 273 15-15 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15-16 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 275 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures MC68HC908AB32 ? rev. 1.0 technical data motorola list of figures 25 figure title page 16-1 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 16-2 spi module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 282 16-3 full-duplex master-slave connections . . . . . . . . . . . . . . . . . 283 16-4 transmission format (cpha = 0) . . . . . . . . . . . . . . . . . . . . . 287 16-5 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16-6 transmission format (cpha = 1) . . . . . . . . . . . . . . . . . . . . . 288 16-7 transmission start delay (master) . . . . . . . . . . . . . . . . . . . . . 290 16-8 sprf/spte cpu interrupt timing . . . . . . . . . . . . . . . . . . . . . 291 16-9 missed read of overflow condition . . . . . . . . . . . . . . . . . . . . 293 16-10 clearing sprf when ovrf interrupt is not enabled . . . . . . 294 16-11 spi interrupt request generation . . . . . . . . . . . . . . . . . . . . . 297 16-12 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16-13 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . 304 16-14 spi status and control register (spscr) . . . . . . . . . . . . . . . 306 16-15 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 17-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 316 17-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 17-5 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 319 17-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 17-8 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17-9 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 321 17-10 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 17-11 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . . 323 17-12 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 324 17-13 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17-14 port d input pullup enable register (ptdpue) . . . . . . . . . . . 325 17-15 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17-16 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 328 17-17 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 17-18 port f data register (ptf). . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17-19 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . . . 330 17-20 port f i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data MC68HC908AB32 ? rev. 1.0 26 list of figures motorola figure title page 17-21 port f input pullup enable register (ptfpue) . . . . . . . . . . . 332 17-22 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . . . . 333 17-23 data direction register g (ddrg). . . . . . . . . . . . . . . . . . . . . 333 17-24 port g i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17-25 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17-26 data direction register h (ddrh) . . . . . . . . . . . . . . . . . . . . . 336 17-27 port h i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 18-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 341 18-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 341 18-3 irq status and control register (iscr) . . . . . . . . . . . . . . . . 343 19-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19-2 keyboard interrupt block diagram . . . . . . . . . . . . . . . . . . . . . 347 19-3 keyboard status and control register (kbscr) . . . . . . . . . . 350 19-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 351 20-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 20-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . 356 20-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 357 21-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 21-2 lvi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21-3 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 22-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 367 22-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 367 22-3 break status and control register (brkscr). . . . . . . . . . . . 369 22-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 370 22-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 370 22-6 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . . 371 22-7 sim break flag control register (sbfcr) . . . . . . . . . . . . . . 372 23-1 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23-2 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 24-1 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 388 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola list of tables 27 technical data ?MC68HC908AB32 list of tables table title page 1-1 i/o pins summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1-2 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1-3 clock source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5-1 eeprom array address blocks. . . . . . . . . . . . . . . . . . . . . . . . 73 5-2 eeprom program/erase mode select . . . . . . . . . . . . . . . . . . 78 7-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8-1 signal naming conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-3 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8-4 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9-1 vco frequency multiplier (n) selection. . . . . . . . . . . . . . . . . 149 10-1 monitor mode entry conditions . . . . . . . . . . . . . . . . . . . . . . . 160 10-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-3 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 163 10-4 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 164 10-5 iread (indexed read) command . . . . . . . . . . . . . . . . . . . . . 164 10-6 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 165 10-7 readsp (read stack pointer) command . . . . . . . . . . . . . . . 165 10-8 run (run user program) command . . . . . . . . . . . . . . . . . . . 166 10-9 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 166 11-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 191 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data MC68HC908AB32 ? rev. 1.0 28 list of tables motorola table title page 12-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 217 13-1 pit prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 14-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15-2 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 15-3 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 15-4 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15-5 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15-6 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15-7 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 15-8 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . . 277 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 16-2 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16-3 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16-4 spi master baud rate selection . . . . . . . . . . . . . . . . . . . . . . 308 17-1 port control register bits summary. . . . . . . . . . . . . . . . . . . . 314 17-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 17-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17-4 port c pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 17-5 port d pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 17-6 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17-7 port f pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 17-8 port g pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17-9 port h pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 19-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21-1 lviout bit indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 25-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola general description 29 technical data ?MC68HC908AB32 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 34 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 35 1.6.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.7 analog ground pin (a vss /v refl ). . . . . . . . . . . . . . . . . . . . . 35 1.6.8 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . 36 1.6.9 analog supply pin (v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . 36 1.6.11 port a input/output (i/o) pins (pta7?ta0) . . . . . . . . . . . . 36 1.6.12 port b i/o pins (ptb7/atd7?tb0/atd0) . . . . . . . . . . . . . 36 1.6.13 port c i/o pins (ptc5?tc0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.14 port d i/o pins (ptd7?td0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.15 port e i/o pins (pte7/spsck?te0/txd) . . . . . . . . . . . . . 37 1.6.16 port f i/o pins (ptf7?tf0/tach2) . . . . . . . . . . . . . . . . . 37 1.6.17 port g i/o pins (ptg2/kbd2?tg0/kbd0) . . . . . . . . . . . . 37 1.6.18 port h i/o pins (pth1/kbd4?th0/kbd3). . . . . . . . . . . . . 37 1.7 i/o pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.8 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.9 clock source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908AB32 ? rev. 1.0 30 general description motorola 1.2 introduction the MC68HC908AB32 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus) with embedded eeprom for user data storage. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the MC68HC908AB32 include the following: high-performance m68hc08 architecture fully upward-compatible object code with m6805, m146805, and m68hc05 families memory map and pin functions compatible with mc68hc08ab32 and mc68hc08ab16 8-mhz internal bus frequency 32k-bytes user program flash memory with security 1 feature 512 bytes of on-chip eeprom with security feature 1k-byte of on-chip ram clock generator module (cgm) two 16-bit, 4-channel timer interface modules (tima and timb) with selectable input capture, output compare, and pwm capability on each channel programmable interrupt timer (pit) serial peripheral interface module (spi) serial communications interface module (sci) 8-channel. 8-bit analog-to-digital converter (adc) low-power design (fully static with stop and wait modes) master reset pin and power-on reset 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mcu block diagram MC68HC908AB32 ? rev. 1.0 technical data motorola general description 31 51 general-purpose input/output (i/o) pins: 30 shared-function i/o pins 5-bit keyboard wakeup port selectable pullups on inputs on port d and port f system protection features optional computer operating properly (cop) reset low-voltage detection with optional reset illegal opcode detection with optional reset illegal address detection with optional reset 64-pin quad flat pack (qfp) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the MC68HC908AB32. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908AB32 ? rev. 1.0 32 general description motorola figure 1-1. MC68HC908AB32 block diagram clock generator module system integration module serial peripheral 4-channel timer interface module b low-voltage inhibit module keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ?80 bytes user flash ?32, 256 bytes user ram ?1024 bytes monitor rom ?307 bytes user flash vectors ?48 bytes single external irq module porta ddra ddre porte internal bus osc1 osc2 cgmxfc * rst * irq interface module interrupt module computer operating properly module pta7 ?pta0 v refh pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tach1 pte2/tach0 pte1/rxd pte0/txd a vss /v refl 4-channel timer interface module a 4.9125-mhz oscillator phase-locked loop serial communications interface module power-on reset module power v ss v dd v ssa v dda ? ports are software configurable with pullup device if input port. ?higher current drive port pins * pin contains integrated pullup device ** pullup enabled when configured as keyboard interrupt pin v ddaref 8-bit analog-to-digital converter module user eeprom ?512 bytes programmable interrupt timer module portb ddrb ptb7/atd7 ?ptb0/atd0 portc ddrc ptc5 ?ptc0 portd ddrd ptd7 ?ptd0 ? ddrf portf ptf7 ? ptf6 ? ptf5/tbch1 ? ptf4/tbch0 ? ptf3/tbch3 ? ptf2/tbch2 ? ptf1/tach3 ? ptf0/tach2 ? portg ddrg ptg2/kbd2 ?ptg0/kbd0 ** porth ddrh pth1/kbd4 ?pth0/kbd3 ** (ptc2/mclk) (ptd6/taclk) (ptd4/tbclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC908AB32 ? rev. 1.0 technical data motorola general description 33 1.5 pin assignments figure 1-2 shows the pin assignment for the MC68HC908AB32. figure 1-2. 64-pin qfp pin assignment ptf7 ptf4/tbch0 cgmxfc ptb7/atd7 ptf3/tbch3 ptf2/tbch2 ptf1/tach3 ptf0/tach2 rst irq ptc4 nc ptf5/tbch1 ptf6 pte0/txd pte1/rxd pte2/tach0 pte3/tach1 pth0/kbd3 ptd3 ptd2 a vss /vrefl v ddaref ptd1 ptd0 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda vrefh ptd7 ptd6/taclk ptd5 ptd4/tbclk pth1/kbd4 ptc5 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd ptg0/kbd0 ptg1/kbd1 ptg2/kbd2 pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908AB32 ? rev. 1.0 34 general description motorola 1.6 pin functions description of pin functions are provided here. 1.6.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-3 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. figure 1-3. power supply bypassing v ss is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (spi). see section 16. serial peripheral interface module (spi) . v ss must be grounded for proper mcu operation. mcu v dd c2 c1 0.1 m f v ss v dd + note: component values shown represent typical applications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions MC68HC908AB32 ? rev. 1.0 technical data motorola general description 35 1.6.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. see section 9. clock generator module (cgm) . 1.6.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pullup resistor. see section 8. system integration module (sim) . 1.6.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. this pin contains an internal pullup resistor. see section 18. external interrupt (irq) . 1.6.5 analog power supply pin (v dda ) v dda is the power supply pin for the clock generator module (cgm). 1.6.6 analog ground pin (v ssa ) the v ssa analog ground pin is used only for the ground connections for the clock generator module (cgm) section of the circuit and should be decoupled as per the v ss digital ground pin. see section 9. clock generator module (cgm) . 1.6.7 analog ground pin (a vss /vrefl) the a vss analog ground pin is used only for the ground connections for the analog to digital convertor (adc) and should be decoupled as per the v ss digital ground pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908AB32 ? rev. 1.0 36 general description motorola 1.6.8 adc voltage reference pin (vrefh) vrefh is the power supply for setting the reference voltage vrefh. connect this pin to a voltage such that 1.5v < vrefh v ddaref . 1.6.9 analog supply pin (v ddaref ) the v ddaref analog supply pin is used only for the supply connections for the analog-to-digital convertor (adc). 1.6.10 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor connection for the cgm. see section 9. clock generator module (cgm) . 1.6.11 port a input/output (i/o) pins (pta7 pta0) pta7?ta0 are general-purpose bidirectional i/o port pins. see section 17. input/output (i/o) ports . 1.6.12 port b i/o pins (ptb7/atd7?tb0/atd0) ptb7?tb0 are special function, bidirectional port pins. ptb7?tb0 are shared with the analog to digital convertor (adc) input pins atd7?td0. see section 14. analog-to-digital converter (adc) and section 17. input/output (i/o) ports . 1.6.13 port c i/o pins (ptc5?tc0) ptc5?tc0 are general-purpose bidirectional i/o port pins. ptc2 is a special function port pin that is shared with the system clock output pin, mclk. see section 17. input/output (i/o) ports . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions MC68HC908AB32 ? rev. 1.0 technical data motorola general description 37 1.6.14 port d i/o pins (ptd7?td0) ptd7?td0 are general-purpose bidirectional i/o port pins. ptd6 and ptd4 are special function port pins that are shared with the timer interface modules (tima and timb). see section 11. timer interface module a (tima) and section 12. timer interface module b (timb) . 1.6.15 port e i/o pins (pte7/spsck?te0/txd) pte7?te0 are special function, bidirectional port pins. pte7?te4 are shared with the serial peripheral interface mode (spi), pte3?te2 are shared with timer a (tima), and pte1?te0 are shared with the serial communications interface (sci). see section 15. serial communications interface module (sci) , section 16. serial peripheral interface module (spi) , section 11. timer interface module a (tima) , and section 17. input/output (i/o) ports . 1.6.16 port f i/o pins (ptf7?tf0/tach2) ptf7?tf6 are general-purpose bidirectional i/o port pins. ptf5?tf0 are special function, bidirectional port pins. ptf5?tf2 are shared with timer b (timb), and ptf1?tf0 are shared with timer a (tima). see section 11. timer interface module a (tima) , section 12. timer interface module b (timb) , and section 17. input/output (i/o) ports . 1.6.17 port g i/o pins (ptg2/kbd2?tg0/kbd0) ptg2?tg0 are general-purpose bidirectional i/o pins with keyboard wakeup function. see section 19. keyboard interrupt module (kbi) and section 17. input/output (i/o) ports . 1.6.18 port h i/o pins (pth1/kbd4?th0/kbd3) pth1?th0 are general-purpose bidirectional i/o pins with keyboard wakeup function. see section 19. keyboard interrupt module (kbi) and section 17. input/output (i/o) ports . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908AB32 ? rev. 1.0 38 general description motorola 1.7 i/o pin summary table 1-1. i/o pins summary pin name function driver type hysteresis reset state pta7?ta0 general purpose i/o dual state no input (hi-z) ptb7/atd7?tb0/atd0 general purpose i/o / adc channel dual state no input (hi-z) ptc5?tc3 general purpose i/o dual state no input (hi-z) ptc2/mclk general purpose i/o / system clock dual state no input (hi-z) ptc1?tc0 general purpose i/o dual state no input (hi-z) ptd7 general purpose i/o dual state no input (hi-z) ptd6/taclk general purpose i/o / timer external input clock dual state no input (hi-z) ptd5 general purpose i/o dual state no input (hi-z) ptd4/tbclk general purpose i/o / timer external input clock dual state no input (hi-z) ptd3?td0 general purpose i/o dual state no input (hi-z) pte7/spsck general purpose i/o / spi clock dual state (open drain) yes input (hi-z) pte6/mosi general purpose i/o / spi data path dual state (open drain) yes input (hi-z) pte5/miso general purpose i/o / spi data path dual state (open drain) yes input (hi-z) pte4/ss general purpose i/o / spi slave select dual state yes input (hi-z) pte3/tach1 general purpose i/o / timer a channel 1 dual state yes input (hi-z) pte2/tach0 general purpose i/o / timer a channel 0 dual state yes input (hi-z) pte1/rxd general purpose i/o / sci receive data dual state yes input (hi-z) pte0/txd general purpose i/o / sci transmit data dual state yes input (hi-z) ptf7?tf6 general purpose i/o dual state yes input (hi-z) ptf5/tbch1 general purpose i/o / timer b channel 1 dual state yes input (hi-z) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description i/o pin summary MC68HC908AB32 ? rev. 1.0 technical data motorola general description 39 details of the clock connections to each of the modules on the MC68HC908AB32 are shown in table 1-2 . a short description of each clock source is also given in table 1-3 . ptf4/tbch0 general purpose i/o / timer b channel 0 dual state yes input (hi-z) ptf3/tbch3 general purpose i/o / timer b channel 3 dual state yes input (hi-z) ptf2/tbch2 general purpose i/o / timer b channel 2 dual state yes input (hi-z) ptf1/tach3 general purpose i/o / timer a channel 3 dual state yes input (hi-z) ptf0/tach2 general purpose i/o / timer a channel 2 dual state yes input (hi-z) ptg2/kbd2?tg0/kbd0 general purpose i/o with key wakeup feature dual state yes input (hi-z) pth1/kbd4?th0/kbd3 general purpose i/o with key wakeup feature dual state yes input (hi-z) v dd logical chip power supply na na na v ss logical chip ground na na na v dda analog power supply (cgm) na na na v ssa analog ground (cgm) na na na v refh adc reference voltage na na na a vss /v refl adc ground and reference voltage na na na v ddaref adc power supply na na na osc1 external clock in na na input (hi-z) osc2 external clock out na na output cgmxfc pll loop ?ter cap na na na irq external interrupt request na na input (pullup) rst reset na na input (pullup) table 1-1. i/o pins summary pin name function driver type hysteresis reset state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data MC68HC908AB32 ? rev. 1.0 40 general description motorola 1.8 signal name conventions 1.9 clock source summary table 1-2. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmout pll-based or osc1-based clock output from cgm module) bus clock cgmout divided by two spsck spi serial clock (see 16.13.3 spsck (serial clock) ) taclk external clock input for tima (see 11.9.1 tima clock pin ) tbclk external clock input for timb (see 12.9.1 timb clock pin ) table 1-3. clock source summary module clock source adc cgmxclk or bus clock cop cgmxclk cpu bus clock eeprom cgmxclk or bus clock rom bus clock ram bus clock spi spsck sci cgmxclk tima bus clock or ptd6/taclk timb bus clock or ptd4/tbclk pit bus clock kbi bus clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 41 technical data ?MC68HC908AB32 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 32, 256 bytes of user flash memory 512 bytes of eeprom 1024 bytes of random-access memory (ram) 48 bytes of user-defined vectors 307 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 42 memory map motorola 2.4 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2.5 input/output (i/o) section most of the control, status, and data registers are in the zero page $0000?004f. additional i/o registers have the following addresses: $fe00; sim break status register, sbsr $fe01; sim reset status register, srsr $fe03; sim break flag control register, sbfcr $fe08; flash control register, flcr $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; lvi status register, lvisr $fe10; eeprom divider non-volatile register high, eedivhnvr $fe11; eeprom divider non-volatile register low, eedivlnvr $fe1a; eeprom timebase divider register high, eedivh $fe1b; eeprom timebase divider register low, eedivl $fe1c; eeprom non-volatile register, eenvr $fe1d; eeprom control register, eecr $fe1f; eeprom array configuration register, eeacr $ff7e; flash block protect register, flbpr $ffff; cop control register, copctl data registers are shown in figure 2-2 , table 2-1 is a list of vector locations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 43 $0000 i/o registers 80 bytes $004f $0050 ram 1,024 bytes $044f $0450 unimplemented 176 bytes $04ff $0500 reserved 128 bytes $057f $0580 unimplemented 640 bytes $07ff $0800 eeprom 512 bytes $09ff $0a00 unimplemented 30,208 bytes $7fff $8000 flash memory 32,256 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 $fe07 reserved 4 bytes $fe08 flash control register (flcr) figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 44 memory map motorola $fe09 $fe0b reserved 3 bytes $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 eeprom divider non-volatile register high (eedivhnvr) $fe11 eeprom divider non-volatile register low (eedivlnvr) $fe12 $fe19 reserved 8 bytes $fe1a eeprom timebase divider register high (eedivh) $fe1b eeprom timebase divider register low (eedivl) $fe1c eeprom non-volatile register (eenvr) $fe1d eeprom control register (eecr) $fe1e reserved $fe1f eeprom array configuration register (eeacr) $fe20 monitor rom 307 bytes $ff52 $ff53 unimplemented 43 bytes $ff7d $ff7e flash block protect register (flbpr) $ff7f unimplemented 65 bytes $ffbf $ffc0 reserved flash memory 16 bytes reserved for compatibility with hc08ab16/24/32 $ffcf $ffd0 flash vectors 48 bytes $ffff figure 2-1. memory map (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 45 addr. register name bit 7 654321 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 $0006 data direction register c (ddrc) read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 46 memory map motorola $000a port g data register (ptg) read: 00000 ptg2 ptg1 ptg0 write: reset: unaffected by reset $000b port h data register (pth) read: 000000 pth1 pth0 write: reset: unaffected by reset $000c data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 $000d data direction register f (ddrf) read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 00000000 $000e data direction register g (ddrg) read: 00000 ddrg2 ddrg1 ddrg0 write: reset: 00000000 $000f data direction register h (ddrh) read: 000000 ddrh1 ddrh0 write: reset: 00000000 $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 00001000 $0012 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 47 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 $0015 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset: unaffected unaffected 000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 11000000 $0017 sci status register 2 (scs2) read: 000000bkfrpf write: reset: 00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 $001a irq status and control register (iscr) read: 0000 irqf 0 imask mode write: ack reset: 00000000 $001b keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset: 00101111 $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 48 memory map motorola $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 $001f configuration register 1 (config1) ? read: lvistop r lvirstd lvipwrd ssrec coprs stop copd write: reset: 00000000 ? one-time writable register after each reset. $0020 timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $0021 keyboard interrupt enable register (kbier) read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 $0022 timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $0023 timer a counter register low (tacntl) read: bit 7 654321 bit 0 write: reset: 00000000 $0024 timer a counter modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $0025 timer a counter modulo register low (tamodl) read: bit 7 654321 bit 0 write: reset: 11111111 $0026 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0027 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 49 $0028 timer a channel 0 register low (tach0l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0029 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 $002a timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b timer a channel 1 register low (tach1l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $002c timer a channel 2 status and control register (tasc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 $002d timer a channel 2 register high (tach2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e timer a channel 2 register low (tach2l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $002f timer a channel 3 status and control register (tasc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 $0030 timer a channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 timer a channel 3 register low (tach3l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 50 memory map motorola $0032 timer b channel 2 status and control register (tbsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 $0033 timer b channel 2 register high (tbch2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 timer b channel 2 register low (tbch2l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0035 timer b channel 3 status and control register (tbsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 $0036 timer b channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 timer b channel 3 register low (tbch3l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0038 analog-to-digital status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset: 00011111 $0039 analog-to-digital data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: 00000000 $003a analog-to-digital clock register (adclk) read: adiv2 adiv1 adiv0 adiclk 0000 write: reset: 00000000 $003b reserved read: rrrrrrrr write: reset: addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 51 $003c reserved read: rrrrrrrr write: reset: $003d port d input pullup enable register (ptdpue) read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset: 00000000 $003e port f input pullup enable register (ptfpue) read: ptfpue7 ptfpue6 ptfpue5 ptfpue4 ptfpue3 ptfpue2 ptfpue1 ptfpue0 write: reset: 00000000 $003f configuration register 2 (config2) ? read: r eedivclk rrrrrr write: reset: 0 ? one-time writable register after each reset. $0040 timer b status and control register (tbsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $0041 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $0042 timer b counter register low (tbcntl) read: bit 7 654321 bit 0 write: reset: 00000000 $0043 timer b counter modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $0044 timer b counter modulo register low (tbmodl) read: bit 7 654321 bit 0 write: reset: 11111111 $0045 timer b channel 0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 52 memory map motorola $0046 timer b channel 0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0047 timer b channel 0 register low (tbch0l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0048 timer b channel 1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 $0049 timer b channel 1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004a timer b channel 1 register low (tbch1l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $004b pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset: 00100000 $004c pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $004d pit counter register low (pcntl) read: bit 7 654321 bit 0 write: reset: 00000000 $004e pit counter modulo register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $004f pit counter modulo register low (pmodl) read: bit 7 654321 bit 0 write: reset: 11111111 addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 53 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 00000000 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por: 10000000 $fe02 reserved read: rrrrrrrr write: reset: 00000000 $fe03 sim break flag control register (sbfcr) read: bcfe rrrrrrr write: reset: 0 $fe04 reserved read: rrrrrrrr write: reset: $fe05 reserved read: rrrrrrrr write: reset: $fe06 reserved read: rrrrrrrr write: reset: $fe07 reserved read: rrrrrrrr write: reset: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset: 00000000 $fe09 reserved read: rrrrrrrr write: reset: addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 54 memory map motorola $fe0a reserved read: rrrrrrrr write: reset: $fe0b reserved read: rrrrrrrr write: reset: $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $fe0d break address register low (brkl) read: bit 7 654321 bit 0 write: reset: 00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset: 00000000 $fe0f low-voltage inhibit status register (lvisr) read: lviout 0000000 write: reset: 00000000 $fe10 eediv non-volatile register high (eedivhnvr)* read: eedivsecd rrrr eediv10 eediv9 eediv8 write: reset: unaffected by reset; $ff when blank $fe11 eediv non-volatile register low (eedivlnvr)* read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank * non-volatile flash register; write by programming. $fe1a ee divider register high (eedivh) read: eedivsecd rrrr eediv10 eediv9 eediv8 write: reset: contents of eedivhnvr ($fe10) $fe1b ee divider register low (eedivl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 10 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC908AB32 ? rev. 1.0 technical data motorola memory map 55 $fe1c eeprom non-volatile register (eenvr)* read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank $fe1d eeprom control register (eecr) read: eedum 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset: 00000000 $fe1e reserved read: rrrrrrrr write: reset: $fe1f eeprom array configuration register (eeacr) read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) $ff7e flash block protect register (flbpr)* read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset * non-volatile flash register; write by programming. $ffff cop control register (copctl) read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 11 of 11) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data MC68HC908AB32 ? rev. 1.0 56 memory map motorola table 2-1. vector addresses vector priority address vector lowest $ffd0 adc conversion complete vector (high) $ffd1 adc conversion complete vector (low) $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) $ffd5 sci transmit vector (low) $ffd6 sci receive vector (high) $ffd7 sci receive vector (low) $ffd8 sci error vector (high) $ffd9 sci error vector (low) $ffda reserved $ffdb reserved $ffdc reserved $ffdd reserved $ffde timer b channel 3 vector (high) $ffdf timer b channel 3 vector (low) $ffe0 timer b channel 2 vector (high) $ffe1 timer b channel 2 vector (low) $ffe2 spi transmit vector (high) $ffe3 spi transmit vector (low) $ffe4 spi receive vector (high) $ffe5 spi receive vector (low) $ffe6 timer b over?w vector (high) $ffe7 timer b over?w vector (low) $ffe8 timer b channel 1 vector (high) $ffe9 timer b channel 1 vector (low) $ffea timer b channel 0 vector (high) $ffeb timer b channel 0 vector (low) $ffec timer a over?w vector (high) $ffed timer a over?w vector (low) $ffee timer a channel 3 vector (high) $ffef timer a channel 3 vector (low) $fff0 timer a channel 2 vector (high) $fff1 timer a channel 2 vector (low) $fff2 timer a channel 1 vector (high) $fff3 timer a channel 1 vector (low) $fff4 timer a channel 0 vector (high) $fff5 timer a channel 0 vector (low) $fff6 programmable interrupt timer (high) $fff7 programmable interrupt timer (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) highest $fffe reset vector (high) $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola random-access memory (ram) 57 technical data ?MC68HC908AB32 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2 introduction this section describes the 1024 bytes of ram (random-access memory). 3.3 functional description addresses $0050 through $044f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently access all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) technical data MC68HC908AB32 ? rev. 1.0 58 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola flash memory 59 technical data ?MC68HC908AB32 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.7 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . 63 4.8 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.1 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . 66 4.9 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.10 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 introduction this section describes the operation of the embedded flash memory. this memory can be read, programmed, and erased from a single external supply. the program and erase operations are enabled through the use of an internal charge pump. 4.3 functional description the flash memory is an array of 32,256 bytes with an additional 48 bytes of user vectors and one byte of block protection. an erased bit reads as logic 1 and a programmed bit reads as a logic 0 . memory in the flash array is organized into two rows per page basis. for the 32k word by 8-bit embedded flash memory, the page size is 128 bytes per f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908AB32 ? rev. 1.0 60 flash memory motorola page. hence the minimum erase page size is 128 bytes. program and erase operations are facilitated through control bits in the flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: $8000?fdff; user memory. $ff7e; flash block protect register. $fe08 ; flash control register. $ffdc?ffff; these locations are reserved for user-defined interrupt and reset vectors. programming tools are available from motorola. contact your local motorola representative for more information. note: a security feature prevents viewing of the flash contents. 1 4.4 flash control register the flash control register (flcr) controls flash program and erase operations. hven ?high-voltage enable bit this read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the flash difficult for unauthorized users. address: $fe08 bit 7 654321 bit 0 read: 0000 hven mass erase pgm write: reset: 00000000 figure 4-1. flash control register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash page erase operation MC68HC908AB32 ? rev. 1.0 technical data motorola flash memory 61 mass ?mass erase control bit setting this read/write bit configures the 32k-byte flash array for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected erase ?erase control bit this read/write bit configures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ?program control bit this read/write bit configures the memory for program operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 4.5 flash page erase operation use this step-by-step procedure to erase a page (128 bytes) of flash memory to read as logic 1: 1. set the erase bit, and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address within the page address range desired. 4. wait for a time, t nvs (min. 10 m s) 5. set the hven bit. 6. wait for a time, t erase (min. 1ms) 7. clear the erase bit. 8. wait for a time, t nvh (min. 5 m s) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908AB32 ? rev. 1.0 62 flash memory motorola 9. clear the hven bit. 10. after a time, t rcv (typ. 1 m s), the memory can be accessed again in read mode. note: while these operations must be performed in the order shown, other unrelated operations may occur between the steps. 4.6 flash mass erase operation use this step-by-step procedure to erase entire flash memory to read as logic 1: 1. set both the erase bit, and the mass bit in the flash control register. 2. read from the flash block protect register. 3. write any data to any flash address* within the flash memory address range. 4. wait for a time, t nvs (min. 10 m s) 5. set the hven bit. 6. wait for a time, t merase (min. 4ms) 7. clear the erase bit. 8. wait for a time, t nvhl (min. 100 m s) 9. clear the hven bit. 10. after a time, t rcv (min. 1 m s), the memory can be accessed again in read mode. * when in monitor mode, with security sequence failed (see 10.5 security ), write to the flash block protect register instead of any flash address. note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash program/read operation MC68HC908AB32 ? rev. 1.0 technical data motorola flash memory 63 4.7 flash program/read operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $0080 and $xxc0. use this step-by-step procedure to program a row of flash memory ( figure 4-2 is a flowchart representation): note: in order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read from the flash block protect register. 3. write any data to any flash address within the row address range desired. 4. wait for a time, t nvs (min. 10 m s). 5. set the hven bit. 6. wait for a time, t pgs (min. 5 m s). 7. write data to the flash address to be programmed.* 8. wait for a time, t prog (min. 30 m s). 9. repeat step 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit.* 11. wait for a time, t nvh (min. 5 m s). 12. clear the hven bit. 13. after time, t rcv (min. 1 m s), the memory can be accessed in read mode again. * the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog max. this program sequence is repeated throughout the memory until all data is programmed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908AB32 ? rev. 1.0 64 flash memory motorola note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. see 23.13 flash memory characteristics . 4.8 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. this protection is done by using of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note: in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit when the flbpr is program with all 0?, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1?), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory, address ranges as shown in 4.8.1 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected block of flash memory is prohibited. the flbpr itself can be erased or programmed only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from reset into the monitor mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash block protection MC68HC908AB32 ? rev. 1.0 technical data motorola flash memory 65 figure 4-2. flash programming flowchart set hven bit read the flash block protect register write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908AB32 ? rev. 1.0 66 flash memory motorola 4.8.1 flash block protect register the flash block protect register (flbpr) is implemented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr[7:0] ?flash block protect bits these eight bits represent bits [14:7] of a 16-bit memory address. bit-15 is logic 1 and bits [6:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00 and xx80 (128 bytes page boundaries) within the flash memory. figure 4-4. flash block protect start address address: $ff7e bit 7 654321 bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 4-3. flash block protect register (flbpr) 1 flbpr value 16-bit memory address 0000000 start address of flash block protect f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory wait mode MC68HC908AB32 ? rev. 1.0 technical data motorola flash memory 67 examples of protect start address: 4.9 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will discontinue, and the flash will be on standby mode. 4.10 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will discontinue, and the flash will be on standby mode note: standby mode is the power saving mode of the flash module in which all internal control signals to the flash are inactive and the current consumption of the flash is at a minimum. bpr[7:0] start of address of protect range $00 the entire flash memory is protected. $01 ( 0000 0001 ) $8080 (1 000 0000 1 000 0000) $02 ( 0000 0010 ) $8100 (1 000 0001 0 000 0000) and so on... $fe ( 1111 1110 ) $ff00 (1 111 1111 0 000 0000) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data MC68HC908AB32 ? rev. 1.0 68 flash memory motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 69 technical data ?MC68HC908AB32 section 5. eeprom 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 eeprom timebase requirements . . . . . . . . . . . . . . . . . . . . . 72 5.7 eeprom security options. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.9 eeprom programming and erasing . . . . . . . . . . . . . . . . . . . . 73 5.9.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.9.2 eeprom erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11 eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.1 eeprom control register. . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.2 eeprom array configuration register . . . . . . . . . . . . . . . . 79 5.11.2.1 eeprom non-volatile register . . . . . . . . . . . . . . . . . . . 80 5.11.3 eeprom timebase divider register . . . . . . . . . . . . . . . . . 80 5.11.3.1 eeprom timebase divider non-volatile register . . . . . 82 5.2 introduction this section describes the 512 bytes electrically erasable programmable read-only-memory (eeprom). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 70 eeprom motorola 5.3 features features of the eeprom include the following: 512 bytes non-volatile memory byte, block or bulk erasable operations non-volatile eeprom configuration and block protection options on-chip charge pump for programming/erasing security option addr. register name bit 7 654321 bit 0 $fe10 eediv non-volatile register high (eedivhnvr)* read: eedivsecd rrrr eediv10 eediv9 eediv8 write: reset: unaffected by reset; $ff when blank $fe11 eediv non-volatile register low (eedivlnvr)* read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank $fe1a ee divider register high (eedivh) read: eedivsecd rrrr eediv10 eediv9 eediv8 write: reset: contents of eedivhnvr ($fe10) $fe1b ee divider register low (eedivl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) $fe1c eeprom non-volatile register (eenvr)* read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank; factory programmed $10 $fe1d eeprom control register (eecr) read: eedum 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset: 00000000 $fe1f eeprom array configuration register (eeacr) read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) * non-volatile eeprom register; write by programming. = unimplemented r = reserved figure 5-1. eeprom i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom functional description MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 71 5.4 functional description the 512 bytes of eeprom is located at $0800?09ff, and can be programmed or erased without an additional external high voltage supply. the program and erase operations are enabled through the use of an internal charge pump. for each byte of eeprom, the write/erase endurance is 10,000 cycles. 5.5 eeprom configuration the 8-bit eeprom non-volatile register (eenvr) and the 16-bit eeprom timebase divider non-volatile register (eedivnvr) contain the default settings for the following eeprom configurations: security option block protection eeprom timebase reference eenvr and eedivnvr are non-volatile, eeprom registers. they are programmed and erased in the same way as eeprom bytes. the contents of these registers are loaded into their respective volatile registers during a mcu reset. the values in these read/write, volatile registers define the eeprom configurations. for eenvr, the corresponding volatile register is the eeprom array configuration register (eeacr). for the eedivnvr (two 8-bit registers: eedivhnvr and eedivlnvr), the corresponding volatile register is the eeprom timebase divider register (eediv: eedivh and eedivl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 72 eeprom motorola 5.6 eeprom timebase requirements a 35 m s timebase is required by the eeprom control circuit for program and erase of eeprom content. this timebase is derived from dividing the cgmxclk or bus clock (selected by eedivclk bit in config2 register) using a timebase divider circuit, controlled by the 16-bit eeprom timebase divider register (eedivh and eedivl). as the cgmxclk or bus clock is user selected, the eeprom timebase divider register must be configured with the appropriate value to obtain the 35 m s. the timebase divider is calculated using the following formula: eediv = int [ reference frequency (hz) 35 10 ? + 0.5 ] this value is written to the eeprom timebase divider register (eedivh and eedivl) or programmed into the eeprom timebase divider non- volatile register prior to any eeprom program or erase operations (see 5.5 eeprom configuration and 5.11.3.1 eeprom timebase divider non-volatile register ). 5.7 eeprom security options the eeprom has a special security option, enabled by programming the eeprtct bit to 0 in the eeprom non-volatile register (eenvr). once security is enabled, the following limitations apply to the eeprom: the 16-byte eeprom locations from $08f0 to $08ff are protected from erase and program operations. the block erase and bulk erase modes are disabled. byte erase can be used for all eeprom locations except $08f0 to $08ff. the eenvr is protected from further erase or program operations. 5.8 eeprom block protection the 512 bytes of eeprom is divided into four 128-byte blocks. each of these blocks can be protected from erase/program operations by setting the eebpx bit in the eenvr. table 5-1 shows the address ranges for the blocks. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom eeprom programming and erasing MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 73 these bits are effective after a reset or a read to eenvr register. the block protect configuration can be modified by erasing/programming the corresponding bits in the eenvr register and then reading the eenvr register. 5.9 eeprom programming and erasing the unprogrammed or erased state of an eeprom bit is a logic 1. the factory default for the eeprom array is $ff for all bytes. the programming operation changes an eeprom bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). in a single programming operation, the minimum eeprom programming size is zero bits; the maximum is eight bits (one byte). the erase operation changes an eeprom bit from logic 0 to logic 1. in a single erase operation, the minimum eeprom erase size is one byte; the maximum is the entire eeprom array. for each eeprom byte, the write/erase endurance is 10,000 cycles. one write/erase cycle is defined as: a maximum of eight programming operations on the same byte followed by an erase operation of the that byte . therefore, it is possible to program a byte, bit by bit to logic 0 before requiring an erase on that byte. note: although programming a bit (from 0 or 1) with a logic 1 does not change the state of that bit, it is still regarded as a programming operation. that is, if the same byte is programmed eight times (with any value), that byte must be erased before it can be successfully programmed again. table 5-1. eeprom array address blocks block number (eebpx) address range eebp0 $0800?087f eebp1 $0880?08ff eebp2 $0900?097f eebp3 $0980?09ff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 74 eeprom motorola 5.9.1 eeprom programming the unprogrammed or erased state of an eeprom bit is a logic 1. programming changes the state to a logic 0. only eeprom bytes in the non-protected blocks and the eenvr register can be programmed. use the following procedure to program a byte of eeprom: 1. clear eeras1 and eeras0, and set eelat in the eecr. (a) 2. write the desired data to the desired eeprom address. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the programming voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bit. (e) note: a. eeras1 and eeras0 must be cleared for programming. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom address will be latched. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. b. if more than one valid eeprom writes occur, the last address and data will be latched, overriding the previous address and data. once written data to the desired address, do not read eeprom locations other than the written location. (reading an eeprom location returns the latched data, and causes the read address to be latched.) c. the eepgm bit cannot be set if the eelat bit is cleared or a non- valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom locations, otherwise the current program cycle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom eeprom programming and erasing MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 75 d. the delay time for the eepgm bit to be cleared in auto mode is less than t eepgm . however, on other mcus, this delay time may be different. for forward compatibility, software should not make any dependency on this delay time. e. any attempt to clear both eepgm and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom array. 5.9.2 eeprom erasing the programmed state of an eeprom bit is logic 0. erasing changes the state to a logic 1. only eeprom bytes in the non-protected blocks and eenvr register can be erased. use the following procedure to erase a byte, block, or the entire eeprom: 1. configure eeras1 and eeras0 for byte, block, or bulk erase; set eelat in eecr. (a) 2. byte erase: write any data to the desired address. (b) block erase: write any data to an address within the desired block. (b) bulk erase: write any data to an address within the array. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time: t ebyte for byte erase; t eblock for block erase; t ebulk for bulk erase. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the erasing voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 76 eeprom motorola note: a. setting the eelat bit configures the address and data buses to latch data for erasing the array. only valid eeprom addresses will be latched. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. b. if more than one valid eeprom writes occur, the last address and data will be latched, overriding the previous address and data. once written data to the desired address, do not read eeprom locations other than the written location. (reading an eeprom location returns the latched data, and causes the read address to be latched.) eenvr is not affected by block or bulk erase. c. the eepgm bit cannot be set if the eelat bit is cleared or a non- valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom locations, otherwise the current erase cycle will be unsuccessful. when eepgm is set, the erase mode cannot be changed, and the on-board erasing sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t ebyte / t eblock / t ebulk . however, on other mcus, this delay time may be different. for forward compatibility, software should not make any dependency on this delay time. e. any attempt to clear both eepgm and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom array. 5.10 low power modes the wait and stop instructions can put the mcu in low power consumption standby modes. 5.10.1 wait mode the wait instruction does not affect the eeprom. it is possible to start the program or erase sequence on the eeprom and put the mcu in wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom eeprom registers MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 77 5.10.2 stop mode the stop instruction reduces the eeprom power consumption to a minimum. the stop instruction should not be executed while the programming and erasing sequence is in progress. if stop mode is entered while eelat and eepgm is set, the programming sequence will be stopped and the programming voltage to the eeprom array removed. the programming sequence will be restarted after leaving stop mode; access to the eeprom is only possible after the programming sequence has completed. if stop mode is entered while eelat and eepgm is cleared, the programming sequence will be terminated abruptly. in either case, the data integrity of the eeprom is not guaranteed. 5.11 eeprom registers four i/o registers and three non-volatile registers control program, erase, and options of the eeprom array. 5.11.1 eeprom control register this read/write register controls programming/erasing of the eeprom array. eedum ?dummy bit this read/write bit has no function. address: $fe1d bit 7 654321 bit 0 read: eedum 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset: 00000000 figure 5-2. eeprom control register (eecr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eep r om t echnical data MC68HC908AB32 ? r e v . 1.0 78 eeprom motorola eeoff ?eeprom power-off this read/write bit disables the eeprom module for lower power consumption. any attempts to access the array will give unpredictable results. reset clears this bit. 1 = disable eeprom array 0 = enable eeprom array eeras[1:0] ?erase/program mode select bits these read/write bits set the erase modes. reset clears these bits. eelat ?eeprom latch control this read/write bit latches the address and data buses for programming the eeprom array. eelat can not be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom program or erase operation 0 = buses configured for normal operation auto ?automatic termination of program/erase cycle when auto is set, eepgm is cleared automatically after the program/erase cycle is terminated by the internal timer. (see note d for 5.9.1 eeprom programming and 5.9.2 eeprom erasing .) 0 = automatic clear of eepgm is disabled 1 = automatic clear of eepgm is enabled t able 5-2 . eep r om p r ogram/erase mode select eebpx eeras1 eeras0 mode 0 0 0 byte program 0 0 1 byte erase 0 1 0 blo c k erase 0 1 1 bulk erase 1 x x no erase/program x = don? care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom eeprom registers MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 79 eepgm ?eeprom program/erase enable this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom array if the eelat bit is set and a write to a valid eeprom location has occurred. reset clears the eepgm bit. 1 = eeprom programming/erasing power switched on 0 = eeprom programming/erasing power switched off note: writing 0s to both the eelat and eepgm bits with a single instruction will only clear eepgm. this is to allow time for the removal of high voltage. 5.11.2 eeprom array configuration register the eeprom array configuration register configures eeprom security and eeprom block protection. this read-only register is loaded with the contents of the eeprom non- volatile register (eenvr) after a reset. con[3:1] ?unused eeprtct ?eeprom protection bit the eeprtct bit is used to enable the security feature in the eeprom (see 5.7 eeprom security options ). 1 = eeprom security disabled 0 = eeprom security enabled address: $fe1f bit 7 654321 bit 0 read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) figure 5-3. eeprom array configuration register (eeacr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 80 eeprom motorola eebp[3:0] ?eeprom block protection bits these bits prevent blocks of eeprom array from being programmed or erased. 1 = eeprom array block is protected 0 = eeprom array block is unprotected 5.11.2.1 eeprom non-volatile register the contents of this register is loaded into the eeprom array configuration register (eeacr) after a reset. this register is erased and programmed in the same way as an eeprom byte. note: the eenvr is factory programmed with $10. 5.11.3 eeprom timebase divider register the 16-bit eeprom timebase divider register consists of two 8-bit registers: eedivh and eedivl. the 11-bit value in this register is used to configure the timebase divider circuit to obtain the 35 m s timebase for eeprom control. block number (eebpx) address range eebp0 $0800?087f eebp1 $0880?08ff eebp2 $0900?097f eebp3 $0980?09ff address: $fe1c bit 7 654321 bit 0 read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank; factory programmed $10 note: non-volatile eeprom register; write by programming. figure 5-4. eeprom non-volatile register (eenvr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom eeprom registers MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 81 these two read/write registers are respectively loaded with the contents of the eeprom timebase divider non-volatile registers (eedivhnvr and eedivlnvr) after a reset. eedivsecd ?eeprom divider security disable this bit enables/disables the security feature of the eediv registers. when eediv security feature is enabled, the state of the registers eedivh and eedivl are locked (including this eedivsecd bit). the eedivhnvr and eedivlnvr non-volatile memory registers are also protected from being erased/programmed. 1 = eediv security feature disabled 0 = eediv security feature enabled eediv[10:0] ?eeprom timebase prescaler these prescaler bits store the value of eediv which is used as the divisor to derive a timebase of 35 m s from the selected reference clock source (cgmxclk or bus clock, see 6.5 configuration register 2 ) for the eeprom related internal timer and circuits. eediv[10:0] bits are readable at any time. they are writable when eelat=0 and eedivsecd=1. address: $fe1a bit 7 654321 bit 0 read: eedivsecd rrrr eediv10 eediv9 eediv8 write: reset: contents of eedivhnvr ($fe10) figure 5-5. eeprom divider register high (eedivh) address: $fe1b bit 7 654321 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) figure 5-6. eeprom divider register low (eedivl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 82 eeprom motorola the eediv value is calculated by the following formula: eediv = int [ reference frequency (hz) 35 10 ? + 0.5 ] where the result inside the bracket is rounded down to the nearest integer value. for example, if the reference frequency is 4.9152mhz, the eediv value is 172. note: programming/erasing the eeprom with an improper eediv value may result in data lost and reduce endurance of the eeprom device. 5.11.3.1 eeprom timebase divider non-volatile register the 16-bit eeprom timebase divider non-volatile register consists of two 8-bit registers: eedivhnvr and eedivlnvr. the contents of these two registers are respectively loaded into the eeprom timebase divider registers, eedivh and eedivl, after a reset. these two registers are erased and programmed in the same way as an eeprom byte. address: $fe10 bit 7 654321 bit 0 read: eedivsecd rrrr eediv10 eediv9 eediv8 write: reset: unaffected by reset; $ff when blank figure 5-7. eeprom divider non-volatile register high(eedivhnvr) address: $fe11 bit 7 654321 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank figure 5-8. eeprom divider non-volatile register low (eedivlnvr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom eeprom registers MC68HC908AB32 ? rev. 1.0 technical data motorola eeprom 83 these two registers are protected from erase and program operations if the eedivsecd is set to logic 1 in the eedivh (see 5.11.3 eeprom timebase divider register ), or programmed to a logic 1 in the eedivhnvr. note: once eedivsecd in the eedivhnvr is programmed to 0 and after a system reset, the eediv security feature is permanently enabled because the eedivsecd bit in the eedivh is always loaded with a 0 thereafter. once this security feature is armed, erase and program operations are disabled for eedivhnvr and eedivlnvr. modifications to the eedivh and eedivl registers are also disabled. therefore, care should be taken before programming a value into the eedivhnvr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eeprom technical data MC68HC908AB32 ? rev. 1.0 84 eeprom motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola configuration register (config) 85 technical data ?MC68HC908AB32 section 6. configuration register (config) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2 introduction this section describes the configuration registers, config1 and config2. the configuration registers enable or disable these options: low-voltage inhibit (lvi) in stop mode lvi reset lvi module power stop mode recovery time (32 cgmxclk cycles or 4096 cgmxclk cycles) cop timeout period (2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles) stop instruction computer operating properly module (cop) eeprom reference clock source (cpu bus clock or cgmxclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . con?uration register (config) technical data MC68HC908AB32 ? rev. 1.0 86 configuration register (config) motorola 6.3 functional description the configuration registers are used in the initialization of various options. the configuration registers can be written once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the mcu, it is recommended that these registers be written immediately after reset. the configuration registers are located at $001f and $003f. the configuration register may be read at anytime. 6.4 configuration register 1 lvistop ?lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvistop bit enables the lvi to operate in stop mode. reset clears lvistop. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ?lvi reset disable bit lvirstd disables the reset signal from the lvi module. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi module resets disabled 0 = lvi module resets enabled address: $001f bit 7 654321 bit 0 read: lvistop r lvirstd lvipwrd ssrec coprs stop copd write: reset: 00000000 r = reserved figure 6-1. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) configuration register 1 MC68HC908AB32 ? rev. 1.0 technical data motorola configuration register (config) 87 lvipwrd ?lvi power disable bit lvipwrd disables the lvi module. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi module power disabled 0 = lvi module power enabled ssrec ?short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096 cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note: if using an external crystal oscillator, do not set the ssrec bit. coprs ?cop rate select bit coprs selects the cop timeout period. reset clears coprs. (see section 20. computer operating properly (cop) .) 1 = cop timeout period is 2 18 ?2 4 cgmxclk cycles 0 = cop timeout period is 2 13 ?2 4 cgmxclk cycles stop ?stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ?cop disable bit copd disables the cop module. (see section 20. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled extra care should be exercised when using this emulation part for development of code to be run in rom ab, as or az parts that the options selected by setting the config1 register match exactly the options selected on any rom code request submitted. the enable/disable logic is not necessarily identical in all parts of the ab, as, and az families. if in doubt, check with your local field applications representative. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . con?uration register (config) technical data MC68HC908AB32 ? rev. 1.0 88 configuration register (config) motorola 6.5 configuration register 2 eedivclk ?eeprom timebase divider clock select bit eedivclk selects the reference clock source for the eeprom timebase divider. (see section 5. eeprom .) 1 = cpu bus clock drives the eeprom timebase divider 0 = cgmxclk drives the eeprom timebase divider extra care should be exercised when using this emulation part for development of code to be run in rom ab, as or az parts that the options selected by setting the config2 register match exactly the options selected on any rom code request submitted. the enable/disable logic is not necessarily identical in all parts of the ab, as, and az families. if in doubt, check with your local field applications representative. address: $003f bit 7 654321 bit 0 read: r eedivclk rrrrrr write: reset: 0 r = reserved figure 6-2. configuration register 2 (config2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 89 technical data ?MC68HC908AB32 section 7. central processor unit (cpu) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2 introduction the m68hc08 cpu (central processor unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 90 central processor unit (cpu) motorola 7.3 features object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64k-byte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64k-bytes low-power stop and wait modes 7.4 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 91 figure 7-1. cpu registers 7.4.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two? complement overflow flag v1 1h i nzc h x 0 0 0 0 7 15 15 15 70 bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 92 central processor unit (cpu) motorola 7.4.2 index register the 16-bit index register allows indexed addressing of a 64k-byte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 7.4.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset: 00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 93 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 7.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.4.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and bit 15 1413121110987654321 bit 0 read: write: reset: 0000000011111111 figure 7-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 94 central processor unit (cpu) motorola 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v ?overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ?half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add- with-carry (adc) operation. the half-carry flag is required for binary- coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7 654321 bit 0 read: v1 1h i nzc write: reset: x 1 1x1xxx x = indeterminate figure 7-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 95 i ?interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ?negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ?zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 96 central processor unit (cpu) motorola c ?carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ?such as bit test and branch, shift, and rotate ?also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.5 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.6.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu during break interrupts MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 97 7.6.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 7.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 7.8 instruction set summary 7.9 opcode map see table 7-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 98 central processor unit (cpu) motorola table 7-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp ? (sp) + (16 ?m) imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x ? (h:x) + (16 ?m) imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a ? (a) & (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? (c) = 0 rel 24 rr 3 bclr n , opr clear bit n in m mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 99 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? (c) = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? (z) = 1 rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 0 rel 90 rr 3 bgt opr branch if greater than (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 0 rel 92 rr 3 bhcc rel branch if half carry bit clear pc ? (pc) + 2 + rel ? (h) = 0 rel 28 rr 3 bhcs rel branch if half carry bit set pc ? (pc) + 2 + rel ? (h) = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? (c) | (z) = 0 rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc ? (pc) + 2 + rel ? (c) = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 1 rel 93 rr 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? (c) = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? (c) | (z) = 1 rel 23 rr 3 blt opr branch if less than (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 1 rel 91 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? (i) = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? (n) = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? (i) = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? (z) = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? (n) = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel rel 20 rr 3 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 100 central processor unit (cpu) motorola brclr n , opr , rel branch if bit n in m clear pc ? (pc) + 3 + rel ? (mn) = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc ? (pc) + 3 + rel ? (mn) = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 3 + rel ? (x) ?(m) = $00 pc ? (pc) + 3 + rel ? (a) ?(m) = $00 pc ? (pc) + 2 + rel ? (a) ?(m) = $00 pc ? (pc) + 4 + rel ? (a) ?(m) = $00 dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c ? 0 ?inh 98 1 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m ? $00 a ? $00 x ? $00 h ? $00 m ? $00 m ? $00 m ? $00 001 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 101 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one s complement) m ? (m ) = $ff ?(m) a ? (a ) = $ff ?(m) x ? (x ) = $ff ?(m) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) 0 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ?(m:m + 1) imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a ? (a) ?1 or m ? (m) ?1 or x ? (x) ? 1 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 4 + rel ? (result) 1 0 dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a ? (h:a)/(x) h ? remainder inh 52 7 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 102 central processor unit (cpu) motorola eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a ? (a ? m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n ( n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a ? (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ? ( m:m + 1 ) 0 imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ? (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 103 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right 0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ? (m) source h:x ? (h:x) + 1 (ix+d, dix+) 0 dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ? (x) (a) ??inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two s complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none inh 9d 1 nsa nibble swap a a ? (a[3:0]:a[7:4]) inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a ? (a) | (m) 0 imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ? (sp) ?1 inh 87 2 pshh push h onto stack push (h); sp ? (sp) ?1 inh 8b 2 pshx push x onto stack push (x); sp ? (sp) ?1 inh 89 2 pula pull a from stack sp ? (sp + 1); pull ( a ) inh 86 2 pulh pull h from stack sp ? (sp + 1); pull ( h ) inh 8a 2 pulx pull x from stack sp ? (sp + 1); pull ( x ) inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 104 central processor unit (cpu) motorola ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp ? $ff inh 9c 1 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp ? sp + 1 ; pull ( pch) sp ? sp + 1; pull (pcl) inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c ? 1 ?inh 99 1 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m ? (a) 0 dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ? (h:x) 0 dir 35 dd 4 stop enable irq pin; stop oscillator i ? 0; stop oscillator 0 inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m ? (x) 0 dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 105 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ? (a) ?(m) imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 9 tap transfer a to ccr ccr ? (a) inh 84 2 tax transfer a to x x ? (a) inh 97 1 tpa transfer ccr to a a ? (ccr) inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ?$00 or (x) ?$00 or (m) ?$00 0 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x ? (sp) + 1 inh 95 2 txa transfer x to a a ? (x) inh 9f 1 txs transfer h:x to sp (sp) ? (h:x) ?1 inh 94 2 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 106 central processor unit (cpu) motorola a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u unde?ed h index register high byte v over?w bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (two s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode sign extend ix1 indexed, 8-bit offset addressing mode ? loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit not affected table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola central processor unit (cpu) 107 central processor unit (cpu) opcode map table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3 dir 4 bset0 2 dir 3 bra 2 rel 4 neg 2 dir 1 nega 1 inh 1 negx 1 inh 4 neg 2 ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1 inh 3 bge 2 rel 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 4 sub 3 ix2 5 sub 4 sp2 3 sub 2 ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3 dir 4 bclr0 2 dir 3 brn 2 rel 5 cbeq 3 dir 4 cbeqa 3 imm 4 cbeqx 3 imm 5 cbeq 3 ix1+ 6 cbeq 4 sp1 4 cbeq 2 ix+ 4 rts 1 inh 3 blt 2 rel 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 4 cmp 3 ix2 5 cmp 4 sp2 3 cmp 2 ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3 dir 4 bset1 2 dir 3 bhi 2 rel 5 mul 1 inh 7 div 1 inh 3 nsa 1 inh 2 daa 1 inh 3 bgt 2 rel 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 4 sbc 3 ix2 5 sbc 4 sp2 3 sbc 2 ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3 dir 4 bclr1 2 dir 3 bls 2 rel 4 com 2 dir 1 coma 1 inh 1 comx 1 inh 4 com 2 ix1 5 com 3 sp1 3 com 1ix 9 swi 1 inh 3 ble 2 rel 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 4 cpx 3 ix2 5 cpx 4 sp2 3 cpx 2 ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3 dir 4 bset2 2 dir 3 bcc 2 rel 4 lsr 2 dir 1 lsra 1 inh 1 lsrx 1 inh 4 lsr 2 ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1 inh 2 txs 1 inh 2 and 2 imm 3 and 2 dir 4 and 3 ext 4 and 3 ix2 5 and 4 sp2 3 and 2 ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3 dir 4 bclr2 2 dir 3 bcs 2 rel 4 sthx 2 dir 3 ldhx 3 imm 4 ldhx 2 dir 3 cphx 3 imm 4 cphx 2 dir 1 tpa 1 inh 2 tsx 1 inh 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 4 bit 3 ix2 5 bit 4 sp2 3 bit 2 ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3 dir 4 bset3 2 dir 3 bne 2 rel 4 ror 2 dir 1 rora 1 inh 1 rorx 1 inh 4 ror 2 ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1 inh 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 4 lda 3 ix2 5 lda 4 sp2 3 lda 2 ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3 dir 4 bclr3 2 dir 3 beq 2 rel 4 asr 2 dir 1 asra 1 inh 1 asrx 1 inh 4 asr 2 ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1 inh 1 ta x 1 inh 2 ais 2 imm 3 sta 2 dir 4 sta 3 ext 4 sta 3 ix2 5 sta 4 sp2 3 sta 2 ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3 dir 4 bset4 2 dir 3 bhcc 2 rel 4 lsl 2 dir 1 lsla 1 inh 1 lslx 1 inh 4 lsl 2 ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1 inh 1 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 4 eor 3 ix2 5 eor 4 sp2 3 eor 2 ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3 dir 4 bclr4 2 dir 3 bhcs 2 rel 4 rol 2 dir 1 rola 1 inh 1 rolx 1 inh 4 rol 2 ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1 inh 1 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 4 adc 3 ix2 5 adc 4 sp2 3 adc 2 ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3 dir 4 bset5 2 dir 3 bpl 2 rel 4 dec 2 dir 1 deca 1 inh 1 decx 1 inh 4 dec 2 ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1 inh 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 4 ora 3 ix2 5 ora 4 sp2 3 ora 2 ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3 dir 4 bclr5 2 dir 3 bmi 2 rel 5 dbnz 3 dir 3 dbnza 2 inh 3 dbnzx 2 inh 5 dbnz 3 ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1 inh 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 4 add 3 ix2 5 add 4 sp2 3 add 2 ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3 dir 4 bset6 2 dir 3 bmc 2 rel 4 inc 2 dir 1 inca 1 inh 1 incx 1 inh 4 inc 2 ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1 inh 1 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix d 5 brclr6 3 dir 4 bclr6 2 dir 3 bms 2 rel 3 tst 2 dir 1 tsta 1 inh 1 tstx 1 inh 3 tst 2 ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1 inh 4 bsr 2 rel 4 jsr 2 dir 5 jsr 3 ext 6 jsr 3 ix2 5 jsr 2 ix1 4 jsr 1ix e 5 brset7 3 dir 4 bset7 2 dir 3 bil 2 rel 5 mov 3dd 4 mov 2 dix+ 4 mov 3 imd 4 mov 2 ix+d 1 stop 1 inh * 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 4 ldx 3 ix2 5 ldx 4 sp2 3 ldx 2 ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3 dir 4 bclr7 2 dir 3 bih 2 rel 3 clr 2 dir 1 clra 1 inh 1 clrx 1 inh 3 clr 2 ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1 inh 1 txa 1 inh 2 aix 2 imm 3 stx 2 dir 4 stx 3 ext 4 stx 3 ix2 5 stx 4 sp2 3 stx 2 ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3 dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data MC68HC908AB32 ? rev. 1.0 108 central processor unit (cpu) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 109 technical data ?MC68HC908AB32 section 8. system integration module (sim) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 112 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . 113 8.3.3 clocks in stop and wait modes . . . . . . . . . . . . . . . . . . . . . 113 8.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . 114 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.2.2 computer operating properly (cop) reset . . . . . . . . . 116 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 117 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.5.1 sim counter during power-on reset. . . . . . . . . . . . . . . . . 118 8.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . 118 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 118 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 123 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 110 system integration module (sim) motorola 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 129 8.2 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. together with the cpu, the sim controls all mcu activities. a block diagram of the sim is shown in figure 8-1 . figure 8-2 is a summary of the sim i/o registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals: stop/wait/reset/break entry and recovery internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: acknowledge timing arbitration control timing vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 8-1 shows the internal signal names used in this section. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 111 figure 8-1. sim block diagram table 8-1. signal naming conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) ? 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 112 system integration module (sim) motorola 8.3 sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 8-3 . this clock can come from either an external oscillator or from the on-chip pll. see section 9. clock generator module (cgm) . figure 8-3. cgm clock signals addr. register name bit 7 654321 bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 00000000 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por: 10000000 $fe03 sim break flag control register (sbfcr) read: bcfe rrrrrrr write: reset: 0 = unimplemented r = reserved figure 8-2. sim i/o register summary pll osc1 cgmxclk ? 2 bus clock generators sim cgm sim counter monitor mode clock select circuit cgmvclk bcs ? 2 a b s * cgmout * when s = 1, cgmout = b user mode ptc3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 113 8.3.1 bus timing in user mode , the internal bus frequency is either the crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see section 9. clock generator module (cgm) . 8.3.2 clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 cgmxclk cycle por timeout has been completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. 8.3.3 clocks in stop and wait modes upon exit from stop mode (by an interrupt, break, or reset), the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 8.7.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 8.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 114 system integration module (sim) motorola all of these resets produce the vector $fffe?fff ($fefe?eff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 8.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). (see 8.8 sim registers .) 8.4.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 8-2 for details. figure 8-4 shows the relative timing. figure 8-4. external reset timing 8.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow for resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. see figure 8-5 . an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. see figure 8-6 . note that for lvi or por resets, the sim cycles through 4096 cgmxclk cycles, during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst as shown in figure 8-5 . table 8-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 115 figure 8-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 8-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 8.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: a por pulse is generated the internal reset signal is asserted the sim enables cgmout internal clocks to the cpu and modules are held inactive for 4096 cgmxclk cycles to allow the oscillator to stabilize irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 116 system integration module (sim) motorola the rst pin is driven low during the oscillator stabilization time the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared figure 8-7. por recovery 8.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, a value (any value) should be written to location $ffff. writing to location $ffff clears the cop counter and bits 12 through 4 of the sim counter. the sim counter output, which occurs at least every 2 13 ?2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 117 8.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the configuration register 1 (config1) is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the trip voltage, v lvii . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 8.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the sim counter is 13 bits long and is clocked by the falling edge of cgmxclk. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 118 system integration module (sim) motorola 8.5.1 sim counter during power-on reset the power-on reset (por) module detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation module (cgm) to drive the bus clock state machine. 8.5.2 sim counter during stop mode recovery the sim counter is also used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. 8.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 8.7.2 stop mode for details.) the sim counter is free-running after all reset states. (see 8.4.2 active resets from internal sources for counter control and internal reset recovery sequences.) 8.6 exception control normal, sequential program execution can be changed in three different ways: interrupts maskable hardware cpu interrupts non-maskable software interrupt instruction (swi) reset break interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 119 8.6.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents onto the stack and sets the interrupt mask (i-bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 8-8 shows interrupt entry timing, and figure 8-9 shows interrupt recovery timing. figure 8-8. interrupt entry timing figure 8-9. interrupt recovery timing interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the i-bit is cleared). (see figure 8-10 .) module idb r/w interrupt dummy sp sp ?1 sp ?2 sp ?3 sp ?4 vect h vect l start addr iab dummy pc ?1[7:0] pc ?1[15:8] x a ccr v data h v data l opcode i-bit module idb r/w interrupt sp ?4 sp ?3 sp ?2 sp ?1 sp pc pc + 1 iab ccr a x pc ?1[7:0] pc ?1[15:8] opcode operand i-bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 120 system integration module (sim) motorola figure 8-10. interrupt processing 8.6.1.1 hardware interrupts processing of a hardware interrupt begins after completion of the current instruction. when the instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i-bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. no no no yes no no yes yes as many interrupts i bit set? from reset break i-bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i-bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 121 if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 8-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 8-11. interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 8.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i-bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ?1, as a hardware interrupt does. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 122 system integration module (sim) motorola table 8-3. vector addresses vector priority address vector lowest $ffd0 adc conversion complete vector (high) $ffd1 adc conversion complete vector (low) $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) $ffd5 sci transmit vector (low) $ffd6 sci receive vector (high) $ffd7 sci receive vector (low) $ffd8 sci error vector (high) $ffd9 sci error vector (low) $ffda reserved $ffdb reserved $ffdc reserved $ffdd reserved $ffde timer b channel 3 vector (high) $ffdf timer b channel 3 vector (low) $ffe0 timer b channel 2 vector (high) $ffe1 timer b channel 2 vector (low) $ffe2 spi transmit vector (high) $ffe3 spi transmit vector (low) $ffe4 spi receive vector (high) $ffe5 spi receive vector (low) $ffe6 timer b over?w vector (high) $ffe7 timer b over?w vector (low) $ffe8 timer b channel 1 vector (high) $ffe9 timer b channel 1 vector (low) $ffea timer b channel 0 vector (high) $ffeb timer b channel 0 vector (low) $ffec timer a over?w vector (high) $ffed timer a over?w vector (low) $ffee timer a channel 3 vector (high) $ffef timer a channel 3 vector (low) $fff0 timer a channel 2 vector (high) $fff1 timer a channel 2 vector (low) $fff2 timer a channel 1 vector (high) $fff3 timer a channel 1 vector (low) $fff4 timer a channel 0 vector (high) $fff5 timer a channel 0 vector (low) $fff6 programmable interrupt timer (high) $fff7 programmable interrupt timer (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) highest $fffe reset vector (high) $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 123 8.6.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 8.6.3 break interrupts the break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. see section 22. break module (brk) . the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 8.6.4 status flag protection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ?for example, a read of one register followed by the read or write of another ?are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 124 system integration module (sim) motorola 8.7 low-power modes executing the stop or wait instruction puts the mcu in a low-power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 8.7.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 8-12 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration register 1 (config1) is 0, then the computer operating properly (cop) module is enabled and remains active in wait mode. figure 8-12. wait mode entry timing figure 8-13 and figure 8-14 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 125 figure 8-13. wait recovery from interrupt or break figure 8-14. wait recovery from internal reset 8.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 126 system integration module (sim) motorola a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the sim break status register (sbsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 8-15 shows stop mode entry timing. figure 8-15. stop mode entry timing figure 8-16. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ?1 sp ?2 sp ?3 stop +1 stop recovery period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 127 8.8 sim registers the sim has three memory mapped registers. table 8-4 shows the mapping of these registers. 8.8.1 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from stop or wait mode. sbsw ?sim break stop/wait this status bit is useful in applications requiring a return to stop or wait mode after exiting from a break interrupt. sbsw can be cleared by writing a logic 0 to it. reset clears sbsw. 1 = stop or wait mode was exited by break interrupt 0 = stop or wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. table 8-4. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7 654321 bit 0 read: rrrrrr sbsw r write: note (1) reset: 00000000 r = reserved note: 1. writing a logic 0 clears sbsw. figure 8-17. sim break status register (sbsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 128 system integration module (sim) motorola 8.8.2 sim reset status register this register contains six flags that show the source of the last reset. the sim reset status register can be cleared by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ?power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if stop or wait mode was exited by break. tst lobyte,sp ; if returnlo is not 0, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to stop/wait opcode. return pulh rti ; restore h register. address: $fe01 bit 7 654321 bit 0 read: por pin cop ilop ilad 0 lvi 0 write: reset: 10000000 = unimplemented figure 8-18. sim reset status register (srsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers MC68HC908AB32 ? rev. 1.0 technical data motorola system integration module (sim) 129 pin ?external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ?computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ?illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ?illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ?low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr 8.8.3 sim break flag control register the sim break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ?break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7 654321 bit 0 read: bcfe rrrrrrr write: reset: 0 r = reserved figure 8-19. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data MC68HC908AB32 ? rev. 1.0 130 system integration module (sim) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 131 technical data ?MC68HC908AB32 section 9. clock generator module (cgm) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.4.1 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4.2 phase-locked loop (pll) circuit . . . . . . . . . . . . . . . . . . . 135 9.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 136 9.4.2.3 manual and automatic pll bandwidth modes . . . . . . . 136 9.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 139 9.4.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.4 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 142 9.5.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . 142 9.5.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . 142 9.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 142 9.5.5 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 142 9.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 143 9.5.7 cgm base clock output (cgmout). . . . . . . . . . . . . . . . . 143 9.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 143 9.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 146 9.6.3 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . 148 9.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 132 clock generator module (cgm) motorola 9.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.9 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.10 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . 151 9.10.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . . 152 9.10.2 parametric influences on reaction time. . . . . . . . . . . . . . 153 9.10.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . 154 9.10.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . 155 9.2 introduction this section describes the clock generator module (cgm). the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system integration module (sim) derives the system clocks. cgmout is based on either the crystal clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequency generator designed for use with 1mhz to 8mhz crystals or ceramic resonators. the pll can generate an 8mhz bus frequency without using a higher frequency crystal. 9.3 features features of the cgm include the following: phase-locked loop with output frequency in integer multiples of the crystal reference programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 133 9.4 functional description the cgm consists of three major sub-modules: crystal oscillator circuit which generates the constant crystal frequency clock, cgmxclk. phase-locked loop (pll) which generates the programmable vco frequency clock cgmvclk. base clock selector circuit; this software-controlled circuit selects either cgmxclk divided by two or the vco clock cgmvclk divided by two, as the base clock cgmout. the sim derives the system clocks from cgmout. figure 9-1 shows the structure of the cgm. figure 9-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog ? 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] to sim, sci to sim monitor mode a b s* user mode *when s = 1, cgmout = b osc1 osc2 v dda cgmxfc v ss ptc3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 134 clock generator module (cgm) motorola 9.4.1 crystal oscillator circuit the crystal oscillator circuit consists of an inverting amplifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the output. the simoscen signal from the system integration module (sim) enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to produce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. an externally generated clock can also feed the osc1 pin of the crystal oscillator circuit. for this configuration, the external clock should be connected to the osc1 pin and the osc2 pin allowed to float. addr. register name bit 7 654321 bit 0 $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset: 00101111 $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset: 00000000 $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 = unimplemented figure 9-2. cgm i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 135 9.4.2 phase-locked loop (pll) circuit the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 9.4.2.1 pll circuits the pll consists of the following circuits: voltage-controlled oscillator (vco) modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (4.9152mhz) times a linear factor l, or (l)f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a frequency f rclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency f rdv = f rclk . the vco? output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor n. the divider? output is the vco feedback clock, cgmvdv, running at a frequency f vdv = f vclk /n. (see 9.4.2.4 programming the pll for more information). the phase detector then compares the vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 136 clock generator module (cgm) motorola then slightly alters the dc voltage on the external capacitor connected to cgmxfc based on the width and direction of the correction pulse. the filter can make fast or slow corrections depending on its mode, described in 9.4.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 9.4.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ?in acquisition mode, the filter can make large frequency corrections to the vco. this mode is used at pll start- up or when the pll has suffered a severe noise hit and the resulting vco frequency is much different from the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. see 9.6.2 pll bandwidth control register (pbwc) . tracking mode ?in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. see 9.4.3 base clock selector circuit . the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. 9.4.2.3 manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manually or automatically. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 137 in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode is used also to determine when the vco clock, cgmvclk, is safe to use as the source for the base clock, cgmout. see 9.6.2 pll bandwidth control register (pbwc) . if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll start-up, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. see 9.4.3 base clock selector circuit . if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. (see 9.7 interrupts for information and precautions on using interrupts). the following conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 9.6.2 pll bandwidth control register (pbwc) ) is a read-only indicator of the mode of the filter. (see 9.4.2.2 acquisition and tracking modes ) the acq bit is set when the vco frequency is within a certain tolerance d trk and is cleared when the vco frequency is out of a certain tolerance d unt . (see 9.10 acquisition/lock time specifications ) the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance d lock and is cleared when the vco frequency is out of a certain tolerance d unl . (see 9.10 acquisition/lock time specifications ) cpu interrupts can occur if enabled (pllie = 1) when the pll? lock condition changes, toggling the lock bit. (see 9.6.1 pll control register (pctl) ) the pll also may operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 138 clock generator module (cgm) motorola and require fast start-up. the following conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 9.10 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. 9.4.2.4 programming the pll the following procedure shows how to program the pll. note: the round function in the following equations means that the real number should be rounded to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequency (four times the desired bus frequency). 3. choose a practical pll reference frequency, f rclk . 4. select a vco frequency multiplier, n. f vclkdes 4f busdes = n round f vclkdes f rclk --------------------- - ? ?? = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 139 5. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 6. select a vco linear range multiplier, l. where f nom = 4.9152mhz 7. calculate and verify the adequacy of the vco programmed center-of-range frequency f vrs . f vrs = (l)f nom 8. verify the choice of n and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application? tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . note: exceeding the recommended maximum bus frequency or vco frequency can cause the mcu to ?rash? 9. program the pll registers accordingly: a. in the upper 4 bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower 4 bits of the pll programming register (ppg), program the binary equivalent of l. 9.4.2.5 special programming exceptions the programming method described in 9.4.2.4 programming the pll does not account for two possible exceptions ?a value of zero for n or l is meaningless when used in the equations given. to account for these exceptions: f vclk nf rclk = f bus f vclk () 4 = l round f vclk f nom ------------ - ? ?? = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 140 clock generator module (cgm) motorola a zero value for n is interpreted exactly the same as a value of one. a zero value for l disables the pll and prevents its selection as the source for the base clock. (see 9.4.3 base clock selector circuit ) 9.4.3 base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a zero. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. 9.4.4 cgm external connections in its typical configuration, the cgm requires seven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 9-3 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 141 crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer? data for more information. figure 9-3 also shows the external components for the pll: bypass capacitor, c byp filter capacitor, c f care should be taken with routing in order to minimize signal cross talk and noise. (see 9.10 acquisition/lock time specifications for routing information and more information on the filter capacitor? value and its effects on pll performance). figure 9-3. cgm external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp *r s can be zero (shorted) when used with higher-frequency crystals. refer to manufacturer? data. osc1 osc2 v ssa cgmxfc v dda v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 142 clock generator module (cgm) motorola 9.5 i/o signals the following paragraphs describe the cgm i/o signals. 9.5.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 9.5.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 9.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. a small external capacitor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the c f connection. 9.5.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. the pin should be connected to the same voltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 9.5.5 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator and pll. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 143 9.5.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and is generated directly from the crystal oscillator circuit. figure 9-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at start-up. 9.5.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output (cgmxclk) divided by two or the vco clock (cgmvclk) divided by two. 9.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 9.6 cgm registers the following registers control and monitor operation of the cgm: pll control register (pctl). (see 9.6.1 pll control register (pctl) ) pll bandwidth control register (pbwc). (see 9.6.2 pll bandwidth control register (pbwc) ) pll programming register (ppg). (see 9.6.3 pll programming register (ppg) ) figure 9-4 is a summary of the cgm registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 144 clock generator module (cgm) motorola 9.6.1 pll control register (pctl) the pll control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. addr. register name bit 7 654321 bit 0 $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset: 00101111 $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset: 00000000 $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 = unimplemented notes: 1. when auto = 0, pllie is forced to logic zero and is read-only. 2. when auto = 0, pllf and lock read as logic zero. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic zero and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 9-4. cgm i/o register summary address: $001c bit 7 654321 bit 0 read: pllie pllf pllon bcs 1111 write: reset: 0 0101111 = unimplemented figure 9-5. pll control register (pctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 145 pllie ?pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ?pll interrupt flag bit this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit is set also. pllf always reads as 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. the pllf bit should be cleared by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: the pllf bit should not be inadvertently cleared. any read or read- modify-write operation on the pll control register clears the pllf bit. pllon ?pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). see 9.4.3 base clock selector circuit . reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ?base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmvclk cycles to complete the transition from one source clock to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 146 clock generator module (cgm) motorola the other. during the transition, cgmout is held in stasis. see 9.4.3 base clock selector circuit . reset and the stop instruction clear the bcs bit. 1 = cgmout driven by cgmvclk/2 0 = cgmout driven by cgmxclk/2 note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. see 9.4.3 base clock selector circuit . bits [3:0] ?unimplemented bits these bits provide no function and always read as 1. 9.6.2 pll bandwidth control register (pbwc) the pll bandwidth control register does the following: selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode. address: $001d bit 7 654321 bit 0 read: auto lock acq xld 0000 write: reset: 0 0000000 = unimplemented figure 9-7. pll bandwidth control register (pbwc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 147 auto ?automatic bandwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), the acq bit should be cleared before turning the pll on. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ?lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ?acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ?crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit indicates whether the crystal reference frequency is active or not. to check the status of the crystal reference, the following procedure should be followed: 1. write a 1 to xld. 2. wait 4 n cycles. (n is the vco frequency multiplier.) 3. read xld. 1 = crystal reference is not active 0 = crystal reference is active f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 148 clock generator module (cgm) motorola the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as 0. bits [3:0] ?reserved for test these bits enable test functions not available in user mode. to ensure software portability from development systems to user applications, software should write zeros to bits [3:0] whenever writing to pbwc. 9.6.3 pll programming register (ppg) the pll programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul[7:4] ?multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier, n. (see 9.4.2.1 pll circuits and 9.4.2.4 programming the pll ). a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. reset initializes these bits to $6 to give a default multiply value of 6. address: $001e bit 7 654321 bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1100110 figure 9-8. pll programming register (ppg) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 149 note: the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs[7:4] ?vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency f vrs . (see 9.4.2.1 pll circuits , 9.4.2.4 programming the pll , and 9.6.1 pll control register (pctl) ). vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see 9.4.2.5 special programming exceptions ). a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. (see 9.4.3 base clock selector circuit and 9.4.2.5 special programming exceptions for more information). reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failure of the pll to achieve lock. table 9-1. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 150 clock generator module (cgm) motorola 9.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency- sensitive, interrupts should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select cgmvclk/2 as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 9.8 low-power modes the wait and stop instructions put the mcu in low-power- consumption standby modes. 9.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm during break interrupts MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 151 9.8.2 stop mode when the stop instruction executes, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco clock, cgmvclk, divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the crystal clock, cgmxclk, divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. 9.9 cgm during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see section 8. system integration module (sim) . to allow software to clear status bits during a break interrupt, a 1 should be written to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. 9.10 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensures the highest stability and lowest acquisition/lock times. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 152 clock generator module (cgm) motorola 9.10.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time of the system, within specified tolerances, to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percentage of the step input or when the output settles to the desired value plus or minus a percentage of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0hz to 1mhz, the acquisition time is the time taken for the frequency to reach 1mhz 50khz. 50khz = 5% of the 1mhz step input. if the system is operating at 1mhz and suffers a ?00khz noise hit, the acquisition time is the time taken to return from 900khz to 1mhz 5khz. 5khz = 5% of the 100khz step input. other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. the discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are as follows: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance d trk . acquisition time is based on an initial frequency error, (f des ?f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see 9.4.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 153 lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance d lock . lock time is based on an initial frequency error, (f des ?f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). see 9.4.2.3 manual and automatic pll bandwidth modes . obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 9.10.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of crystal frequency f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. see 9.10.3 choosing a filter capacitor . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 154 clock generator module (cgm) motorola also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 9.10.3 choosing a filter capacitor as described in 9.10.2 parametric influences on reaction time , the external filter capacitor c f is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to the following equation: for the value of v dda , the voltage potential at which the mcu is operating should be used. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonly available capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the pll may become unstable. also, always choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. c f c fact v dda f rdv ------------ - ? ?? = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications MC68HC908AB32 ? rev. 1.0 technical data motorola clock generator module (cgm) 155 9.10.4 reaction time calculation the actual acquisition and lock times can be calculated using the equations below. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f , (see 9.10.3 choosing a filter capacitor ) room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. see 9.4.2.2 acquisition and tracking modes . note the inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode the acquisition and lock times are quantized into units based on the reference frequency. see 9.4.2.3 manual and automatic pll bandwidth modes . a certain number of clock cycles, n acq , is required to ascertain whether the pll is within the tracking mode entry tolerance d trk , before exiting acquisition mode. also, a certain number of clock cycles, n trk , is required to ascertain t acq v dda f rdv ------------ - ? ?? 8 k acq ------------- ? ?? = t al v dda f rdv ------------ - ? ?? 4 k trk ------------ ? ?? = t lock t acq t al + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) technical data MC68HC908AB32 ? rev. 1.0 156 clock generator module (cgm) motorola whether the pll is within the lock mode entry tolerance d lock . therefore, the acquisition time t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time t al , is an integer multiple of n trk /f rdv . also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see 9.4.3 base clock selector circuit ), because the factors described in 9.10.2 parametric influences on reaction time may slow the lock time considerably. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola monitor rom (mon) 157 technical data ?MC68HC908AB32 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.6 extended security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10.2 introduction this section describes the monitor rom (mon). the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908AB32 ? rev. 1.0 158 monitor rom (mon) motorola 10.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial communication between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer 4800 baud to 28.8 k-baud communication with host computer flash memory security feature 1 execution of code in ram or flash 10.4 functional description the monitor rom receives and executes commands from a host computer. figure 10-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the mcu has a flash security feature to prevent external viewing of the contents of flash. proper procedures must be followed to verify flash content. access to the flash is denied to unauthorized users of customer specified software. in monitor mode, the mcu can execute host-computer code in ram while all mcu pins except pta0 retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. 1. no security feature is absolutely secure. however, motorola? strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola monitor rom (mon) 159 figure 10-1. monitor mode circuit + + + + 10 m w x1 v dd v tst mc145407 mc74hc125 rst irq osc1 osc2 v ss v dd pta0 v dd 10 k w 0.1 m f 10 w 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 m f 10 m f 10 m f 10 m f 1 2 4 7 14 3 0.1 m f 4.9152 mhz 10 k w ptc3 v dd 10 k w b a notes: position b ?bus clock = cgmxclk ? 2 (see notes) 5 6 ptc0 ptc1 v dd 10 k w position a ?bus clock = cgmxclk ? 4 or cgmvclk ? 4 v cgmxfc 0.1 m f v dd a v dd a MC68HC908AB32 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908AB32 ? rev. 1.0 160 monitor rom (mon) motorola 10.4.1 entering monitor mode table 10-1 shows the pin conditions for entering monitor mode. enter monitor mode by either executing a software interrupt instruction (swi) or applying a logic 0 and then a logic 1 to the rst pin. the mcu sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the necessary baud rate. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v tst (see section 23. electrical specifications ) is applied to either the irq pin or the rst pin. (see section 8. system integration module (sim) for more information on modes of operation.) note: holding the ptc3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 10-1. monitor mode entry conditions irq pin ptc0 pin ptc1 pin pta0 pin ptc3 pin cgmout bus frequency (cgmout ?2) v tst (1) notes : 1. for v tst , see section 23. electrical specifications . 1011 cgmxclk ?2 or cgmvclk ?2 cgmxclk ?4 or cgmvclk ?4 v tst 1010 cgmxclk cgmxclk ?2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola monitor rom (mon) 161 table 10-2 is a summary of the differences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) the data transmit and receive rate can be anywhere from 4800 baud to 28.8 k-baud. transmit and receive baud rates must be identical. figure 10-2. monitor data format figure 10-3. sample monitor waveforms table 10-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin while in monitor mode, the sim asserts its cop enable output. the cop can be enabled or disabled by the copd bit in the configuration register 1 (config1). (see 23.6 5.0-v dc electrical characteristics .) $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 stop bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908AB32 ? rev. 1.0 162 monitor rom (mon) motorola 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. any result of a command appears after the echo of the last byte of the command. figure 10-4. read transaction 10.4.4 break signal a start bit followed by nine low bits is a break signal. (see figure 10-5 .) when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. figure 10-5. break transaction addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola monitor rom (mon) 163 10.4.5 commands the monitor rom uses these commands: read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program a sequence of iread or iwrite commands can access a block of memory sequentially over the full 64k-byte memory map. table 10-3. read (read memory) command description read byte from memory operand speci?s 2-byte address in high byte:low byte order data returned returns contents of speci?d address opcode $4a command sequence read read echo sent to monitor address high address high address low data return address low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908AB32 ? rev. 1.0 164 monitor rom (mon) motorola table 10-4. write (write memory) command description write byte to memory operand speci?s 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 10-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand speci?s 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo sent to monitor address high address high address low address low data data iread iread echo sent to monitor data return data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola monitor rom (mon) 165 table 10-6. iwrite (indexed write) command description write to last address accessed + 1 operand speci?s single data byte data returned none opcode $19 command sequence table 10-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence iwrite iwrite echo sent to monitor data data readsp readsp echo sent to monitor sp return sp high low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908AB32 ? rev. 1.0 166 monitor rom (mon) motorola 10.4.6 baud rate with a 4.9152-mhz crystal and the ptc3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by the mul[7:4] bits in the pll programming register (ppg). (see section 9. clock generator module (cgm) .) table 10-8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 10-9. monitor baud rate selection monitor baud rate vco frequency multiplier (n) 123456 4.9152 mhz 4800 9600 14,400 19,200 24,000 28,800 4.194 mhz 4096 8192 12,288 16,384 20,480 24,576 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) security MC68HC908AB32 ? rev. 1.0 technical data motorola monitor rom (mon) 167 10.5 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?fffd. locations $fff6?fffd contain user- defined data. note: do not leave locations $fff6?fffd blank. for security reasons, program locations $fff6?fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 10-6 .) figure 10-6. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 cgmxclk cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data MC68HC908AB32 ? rev. 1.0 168 monitor rom (mon) motorola upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. to determine whether the security code entered is correct, check to see if bit 6 of ram address $50 is set. if it is, then the correct security code has been entered and flash can be accessed. note: the mcu does not transmit a break character until after the host sends the eight security bits. if the host fails the security bypass as described in 10.5 security , the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. the mcu monitor commands are still valid and user software can execute from ram. a bulk-erase operation is possible, erasing the entire flash memory, including the security bytes at $fff6?fffd. 10.6 extended security to further disable monitor mode functions, an extended security command keyword can be programmed at flash locations $ffc0?ffc7. the keyword is eight bytes long with a 7-byte ascii string and 1-byte $00 delimiter. the keyword for the MC68HC908AB32 mcu is "pswdopt" + $00. entry to monitor mode with extended security command keyword programmed, the mcu stops communicating with the host after transmitting a break character if the host fails the security bypass as described in 10.5 security . note: once the extended security command keyword is programmed, the flash memory cannot be erased without a valid security code (matching $fff6?fffd). therefore, the extended security command keyword should not be programmed during software development. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 169 technical data ?MC68HC908AB32 section 11. timer interface module a (tima) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . 176 11.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . 177 11.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 178 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 179 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.8 tima during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.9.1 tima clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.9.2 tima channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.10.1 tima status and control register . . . . . . . . . . . . . . . . . . . 184 11.10.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.10.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . 187 11.10.4 tima channel status and control registers . . . . . . . . . . . 188 11.10.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 170 timer interface module a (tima) motorola 11.2 introduction this section describes the timer interface module a (tima). the tima is a four-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 11-1 is a block diagram of the tima. 11.3 features features of the tima include the following: four input capture/output compare channels: rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable tima clock input: seven-frequency internal bus clock prescaler selection external tima clock input (4mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow tima counter stop and reset bits modular architecture expandable to eight channels f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) pin name conventions MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 171 11.4 pin name conventions the tima share five i/o pins with port d, e, and f i/o pins. the full name of the tima i/o pin is listed in table 11-1 . the generic pin name appear in the text that follows. 11.5 functional description figure 11-1 shows the structure of the tima. the central component of the tima is the 16-bit tima counter that can operate as a free-running counter or a modulo up-counter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh:tamodl, control the modulo value of the tima counter. software can read the tima counter value at any time without affecting the counting sequence. the four tima channels are programmable independently as input capture or output compare channels. 11.5.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, ptd6/taclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tima status and control register select the tima clock source. table 11-1. pin name conventions tima generic pin names: full tima pin names: taclk ptd6/taclk tach0 pte2/tach0 tach1 pte3/tach1 tach2 ptf0/tach2 tach3 ptf1/tach3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 172 timer interface module a (tima) motorola figure 11-1. tima block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tach0h:tach0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tach1h:tach1l 16-bit comparator 16-bit latch tach2h:tach2l 16-bit comparator 16-bit latch tach3h:tach3l channel 0 channel 1 channel 2 channel 3 tamodh:tamodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f els2b els2a tov2 ch2ie ch2max ch2f els3b els3a tov3 ch3ie ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus internal ms1a ms2a ms3a ptd6/taclk pte2/tach0 pte3/tach1 ptf0/tach2 ptf1/tach3 interrupt logic pte2 logic interrupt logic interrupt logic pte3 logic interrupt logic ptf0 logic interrupt logic ptf1 logic bus clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 173 addr. register name bit 7 654321 bit 0 $0020 timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $0022 timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $0023 timer a counter register low (tacntl) read: bit 7 654321 bit 0 write: reset: 00000000 $0024 timer a counter modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $0025 timer a counter modulo register low (tamodl) read: bit 7 654321 bit 0 write: reset: 11111111 $0026 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0027 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 timer a channel 0 register low (tach0l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0029 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 $002a timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset = unimplemented figure 11-2. tima i/o register summary (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 174 timer interface module a (tima) motorola 11.5.2 input capture with the input capture function, the tima can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tima latches the contents of the tima counter into the tima channel registers, tachxh:tachxl. the polarity of the active edge is programmable. input captures can generate tima cpu interrupt requests. $002b timer a channel 1 register low (tach1l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $002c timer a channel 2 status and control register (tasc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 $002d timer a channel 2 register high (tach2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e timer a channel 2 register low (tach2l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $002f timer a channel 3 status and control register (tasc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 $0030 timer a channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 timer a channel 3 register low (tach3l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset addr. register name bit 7 654321 bit 0 = unimplemented figure 11-2. tima i/o register summary (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 175 11.5.3 output compare with the output compare function, the tima can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tima can set, clear, or toggle the channel pin. output compares can generate tima cpu interrupt requests. 11.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tima overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tima may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 176 timer interface module a (tima) motorola 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte2/tach0 pin. the tima channel registers of the linked pair alternately control the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 registers initially controls the output on the pte2/tach0 pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (0 or 1) that control the output are the ones written to last. tasc0 controls and monitors the buffered output compare function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the linked pair alternately control the output. setting the ms2b bit in tima channel 2 status and control register (tasc2) links channel 2 and channel 3. the output compare value in the tima channel 2 registers initially controls the output on the ptf0/tach2 pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (2 or 3) that control the output are the ones written to last. tasc2 controls and monitors the buffered output compare function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tach3, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 177 11.5.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between overflows is the period of the pwm signal. as figure 11-3 shows, the output compare value in the tima channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tima to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the tima to set the pin if the state of the pwm pulse is logic zero. figure 11-3pwm period and pulse width the value in the tima counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tima counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 11.10.1 tima status and control register . the value in the tima channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tima channel registers produces a duty cycle of 128/256 or 50%. tachx period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 178 timer interface module a (tima) motorola 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tima overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tima may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 179 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2/tach0 pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the pte2/tach0 pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pulse width are the ones written to last. tasc0 controls and monitors the buffered pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tima channel 2 status and control register (tasc2) links channel 2 and channel 3. the tima channel 2 registers initially control the pulse width on the ptf0/tach2 pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (2 or 3) that control the pulse width are the ones written to last. tasc2 controls and monitors the buffered pwm function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tach3, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 180 timer interface module a (tima) motorola 11.5.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by setting the tima stop bit, tstop. b. reset the tima counter by setting the tima reset bit, trst. 2. in the tima counter modulo registers (tamodh:tamodl), write the value for the required pwm period. 3. in the tima channel x registers (tachxh:tachxl), write the value for the required pulse width. 4. in tima channel x status and control register (tascx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 11-3 . a. write 1 to the toggle-on-overflow bit, tovx. b. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 11-3 . note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima status control register (tasc), clear the tima stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tima channel 0 registers (tach0h:tach0l) initially control the buffered pwm output. tima channel 0 status and control register 0 (tasc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) interrupts MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 181 setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tima channel 2 registers (tach2h:tach2l) initially control the pwm output. tima channel 2 status and control register (tasc2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. see 11.10.4 tima channel status and control registers . 11.6 interrupts the following tima sources can generate interrupt requests: tima overflow flag (tof) ?the tof bit is set when the tima counter value rolls over to $0000 after matching the value in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. tof and toie are in the tima status and control register. tima channel flags (ch3f?h0f) ?the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie= 1. chxf and chxie are in the tima channel x status and control register. 11.7 low-power modes the wait and stop instructions puts the mcu in low-power- consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 182 timer interface module a (tima) motorola 11.7.1 wait mode the tima remains active after the execution of a wait instruction. in wait mode the tima registers are not accessible by the cpu. any enabled cpu interrupt request from the tima can bring the mcu out of wait mode. if tima functions are not required during wait mode, reduce power consumption by stopping the tima before executing the wait instruction. 11.7.2 stop mode the tima is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tima counter. tima operation resumes when the mcu exit stop mode after an external interrupt. 11.8 tima during break interrupts a break interrupt stops the tima counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 8.8.3 sim break flag control register . to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o signals MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 183 11.9 i/o signals ports e and f each share two pins with the tima and port d shares one. ptd6/taclk is an external clock input to the tima prescaler. the four tima channel i/o pins are pte2/tach0, pte3/tach1, ptf0/tach2, and ptf1/tach3. 11.9.1 tima clock pin ptd6/taclk is an external clock input that can be the clock source for the tima counter instead of the prescaled internal bus clock. select the ptd6/taclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. see 11.10.1 tima status and control register . the minimum taclk pulse width, taclk lmin or taclk hmin , is: the maximum taclk frequency is: bus frequency ? 2 ptd6/taclk is available as a general-purpose i/o pin when not used as the tima clock input. when the ptd6/taclk pin is the tima clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 11.9.2 tima channel i/o pins each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptf0/tach2 and pte3/tach1 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------------------------- t su + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 184 timer interface module a (tima) motorola 11.10 i/o registers the following i/o registers control and monitor operation of the tima: tima status and control register (tasc) tima counter registers (tacnth:tacntl) tima counter modulo registers (tamodh:tamodl) tima channel status and control registers (tasc0, tasc1, tasc2, and tasc3) tima channel registers (tach0h:tach0l, tach1h:tach1l, tach2h:tach2l, and tach3h:tach3l) 11.10.1 tima status and control register the tima status and control register does the following: enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock address: $0020 bit 7 654321 bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 11-4. tima status and control register (tasc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 185 tof ?tima overflow flag bit this read/write flag is set when the tima counter resets to $0000 after reaching the modulo value programmed in the tima counter modulo registers. clear tof by reading the tima status and control register when tof is set and then writing a logic zero to tof. if another tima overflow occurs before the clearing sequence is complete, then writing logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = tima counter has reached modulo value 0 = tima counter has not reached modulo value toie ?tima overflow interrupt enable bit this read/write bit enables tima overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ?tima stop bit this read/write bit stops the tima counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note: do not set the tstop bit before entering wait mode if the tima is required to exit wait mode. trst ?tima reset bit setting this write-only bit resets the tima counter and the tima prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tima counter is reset and always reads as logic zero. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 186 timer interface module a (tima) motorola ps[2:0] ?prescaler select bits these read/write bits select either the ptd6/taclk pin or one of the seven prescaler outputs as the input to the tima counter as table 11-2 shows. reset clears the ps[2:0] bits. 11.10.2 tima counter registers the two read-only tima counter registers contain the high and low bytes of the value in the tima counter. reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears the tima counter registers. note: if you read tacnth during a break interrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. table 11-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock ? 1 0 0 1 internal bus clock ? 2 0 1 0 internal bus clock ? 4 0 1 1 internal bus clock ? 8 1 0 0 internal bus clock ? 16 1 0 1 internal bus clock ? 32 1 1 0 internal bus clock ? 64 1 1 1 ptd6/taclk address: $0022 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 = unimplemented figure 11-5. tima counter register high (tacnth) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 187 11.10.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the modulo value, the overflow flag (tof) becomes set, and the tima counter resumes counting from $0000 at the next clock. writing to the high byte (tamodh) inhibits the tof bit and overflow interrupts until the low byte (tamodl) is written. reset sets the tima counter modulo registers. note: reset the tima counter before writing to the tima counter modulo registers. address: $0023 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 = unimplemented figure 11-6. tima counter register low (tacntl) address: $0024 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 figure 11-7. tima counter modulo register high (tamodh) address: $0025 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 11111111 figure 11-8. tima counter modulo register low (tamodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 188 timer interface module a (tima) motorola 11.10.4 tima channel status and control registers each of the tima channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tima overflow selects 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation address: $0026 bit 7 654321 bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 figure 11-9. tima channel 0 status and control register (tasc0) address: $0029 bit 7 654321 bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 figure 11-10. tima channel 1 status and control register (tasc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 189 chxf ?channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tima counter registers matches the value in the tima channel x registers. when tim cpu interrupt requests are enabled (chxie = 1), clear chxf by reading tima channel x status and control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ?channel x interrupt enable bit this read/write bit enables tima cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled address: $002c bit 7 654321 bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 figure 11-11. tima channel 2 status and control register (tasc2) address: $002f bit 7 654321 bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 figure 11-12. tima channel 3 status and control register (tasc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 190 timer interface module a (tima) motorola msxb ?mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tima channel 0 and tima channel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ?mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tbchx pin. see table 11-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tima status and control register (tasc). elsxb and elsxa ?edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to the port i/o, and pin tachx is available as a general-purpose i/o pin. table 11-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 191 note: before enabling a tima channel register for input capture operation, make sure that the tachx pin is stable for at least two bus clocks. tovx ?toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggle on tima counter overflow. note: when tovx is set, a tima counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ?channel x maximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 11-13 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 192 timer interface module a (tima) motorola figure 11-13. chxmax latency 11.10.5 tima channel registers these read/write registers contain the captured tima counter value of the input capture function or the output compare value of the output compare function. the state of the tima channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures until the low byte (tachxl) is read. in output compare mode (msxb:msxa 1 0:0), writing to the high byte of the tima channel x registers (tachxh) inhibits output compares until the low byte (tachxl) is written. output overflow tachx period chxmax overflow overflow overflow overflow compare output compare output compare output compare address: $0027 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-14. tima channel 0 register high (tach0h) address: $0028 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 11-15. tima channel 0 register low (tach0l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module a (tima) 193 address: $002a bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-16. tima channel 1 register high (tach1h) address: $002b bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 11-17. tima channel 1 register low (tach1l) address: $002d bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-18. tima channel 2 register high (tach2h) address: $002e bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 11-19. tima channel 2 register low (tach2l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module a (tima) technical data MC68HC908AB32 ? rev. 1.0 194 timer interface module a (tima) motorola address: $0030 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-20. tima channel 3 register high (tach3h) address: $0031 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 11-21. tima channel 3 register low (tach3l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 195 technical data ?MC68HC908AB32 section 12. timer interface module b (timb) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . 202 12.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . 203 12.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 204 12.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 205 12.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.8 timb during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.9.1 timb clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.9.2 timb channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.10.1 timb status and control register . . . . . . . . . . . . . . . . . . . 210 12.10.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.10.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . 213 12.10.4 timb channel status and control registers . . . . . . . . . . . 214 12.10.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 218 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 196 timer interface module b (timb) motorola 12.2 introduction this section describes the timer interface module a (timb). the timb is a four-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 12-1 is a block diagram of the timb. 12.3 features features of the timb include the following: four input capture/output compare channels: rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable timb clock input: seven-frequency internal bus clock prescaler selection external timb clock input (4mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow timb counter stop and reset bits modular architecture expandable to eight channels f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) pin name conventions MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 197 12.4 pin name conventions the timb share five i/o pins with port d and f i/o pins. the full name of the timb i/o pin is listed in table 12-1 . the generic pin name appear in the text that follows. 12.5 functional description figure 12-1 shows the structure of the timb. the central component of the timb is the 16-bit timb counter that can operate as a free-running counter or a modulo up-counter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh:tbmodl, control the modulo value of the timb counter. software can read the timb counter value at any time without affecting the counting sequence. the four timb channels are programmable independently as input capture or output compare channels. 12.5.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, ptd4/tbclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the timb status and control register select the timb clock source. table 12-1. pin name conventions timb generic pin names: full timb pin names: tbclk ptd4/tbclk tbch0 ptf4/tbch0 tbch1 ptf5/tbch1 tbch2 ptf2/tbch2 tbch3 ptf3/tbch3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 198 timer interface module b (timb) motorola figure 12-1. timb block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tbch0h:tbch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tbch1h:tbch1l 16-bit comparator 16-bit latch tbch2h:tbch2l 16-bit comparator 16-bit latch tbch3h:tbch3l channel 0 channel 1 channel 2 channel 3 tbmodh:tbmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f els2b els2a tov2 ch2ie ch2max ch2f els3b els3a tov3 ch3ie ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus internal ms1a ms2a ms3a ptd4/tbclk ptf4/tbch0 ptf5/tbch1 ptf2/tbch2 t ptf3/tbch3 interrupt logic ptf4 logic interrupt logic interrupt logic ptf5 logic interrupt logic ptf2 logic interrupt logic ptf3 logic bus clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 199 addr. register name bit 7 654321 bit 0 $0040 timer b status and control register (tbsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $0041 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $0042 timer b counter register low (tbcntl) read: bit 7 654321 bit 0 write: reset: 00000000 $0043 timer b counter modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $0044 timer b counter modulo register low (tbmodl) read: bit 7 654321 bit 0 write: reset: 11111111 $0045 timer b channel 0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0046 timer b channel 0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0047 timer b channel 0 register low (tbch0l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0048 timer b channel 1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 $0049 timer b channel 1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset = unimplemented figure 12-2. timb i/o register summary (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 200 timer interface module b (timb) motorola 12.5.2 input capture with the input capture function, the timb can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timb latches the contents of the timb counter into the timb channel registers, tbchxh:tbchxl. the polarity of the active edge is programmable. input captures can generate timb cpu interrupt requests. $004a timer b channel 1 register low (tbch1l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0032 timer b channel 2 status and control register (tbsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 $0033 timer b channel 2 register high (tbch2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 timer b channel 2 register low (tbch2l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset $0035 timer b channel 3 status and control register (tbsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 $0036 timer b channel 3 register high (tbch3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 timer b channel 3 register low (tbch3l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset addr. register name bit 7 654321 bit 0 = unimplemented figure 12-2. timb i/o register summary (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 201 12.5.3 output compare with the output compare function, the timb can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the timb can set, clear, or toggle the channel pin. output compares can generate timb cpu interrupt requests. 12.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 12.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a timb overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the timb may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 202 timer interface module b (timb) motorola 12.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the linked pair alternately control the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 registers initially controls the output on the ptf4/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the output after the timb overflows. at each subsequent overflow, the timb channel registers (0 or 1) that control the output are the ones written to last. tbsc0 controls and monitors the buffered output compare function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/tbch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf2/tbch2 pin. the timb channel registers of the linked pair alternately control the output. setting the ms2b bit in timb channel 2 status and control register (tbsc2) links channel 2 and channel 3. the output compare value in the timb channel 2 registers initially controls the output on the ptf2/tbch2 pin. writing to the timb channel 3 registers enables the timb channel 3 registers to synchronously control the output after the timb overflows. at each subsequent overflow, the timb channel registers (2 or 3) that control the output are the ones written to last. tbsc2 controls and monitors the buffered output compare function, and timb channel 3 status and control register (tbsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf3/tbch3, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 203 12.5.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between overflows is the period of the pwm signal. as figure 12-3 shows, the output compare value in the timb channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the timb to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the timb to set the pin if the state of the pwm pulse is logic zero. figure 12-3pwm period and pulse width the value in the timb counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the timb counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 12.10.1 timb status and control register . the value in the timb channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timb channel registers produces a duty cycle of 128/256 or 50%. tbchx period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 204 timer interface module b (timb) motorola 12.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 12.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a timb overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the timb may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 205 12.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the ptf4/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (0 or 1) that control the pulse width are the ones written to last. tbsc0 controls and monitors the buffered pwm function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/tbch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf2/tbch2 pin. the timb channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in timb channel 2 status and control register (tbsc2) links channel 2 and channel 3. the timb channel 2 registers initially control the pulse width on the ptf2/tbch2 pin. writing to the timb channel 3 registers enables the timb channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (2 or 3) that control the pulse width are the ones written to last. tbsc2 controls and monitors the buffered pwm function, and timb channel 3 status and control register (tbsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf3/tbch3, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 206 timer interface module b (timb) motorola 12.5.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by setting the timb stop bit, tstop. b. reset the timb counter by setting the timb reset bit, trst. 2. in the timb counter modulo registers (tbmodh:tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh:tbchxl), write the value for the required pulse width. 4. in timb channel x status and control register (tbscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 12-3 . a. write 1 to the toggle-on-overflow bit, tovx. b. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 12-3 . note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb status control register (tbsc), clear the timb stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the timb channel 0 registers (tbch0h:tbch0l) initially control the buffered pwm output. timb channel 0 status and control register (tbsc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) interrupts MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 207 setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the timb channel 2 registers (tbch2h:tbch2l) initially control the pwm output. timb channel 2 status and control register (tbsc2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. see 12.10.4 timb channel status and control registers . 12.6 interrupts the following timb sources can generate interrupt requests: timb overflow flag (tof) ?the tof bit is set when the timb counter value rolls over to $0000 after matching the value in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt requests. tof and toie are in the timb status and control register. timb channel flags (ch3f?h0f) ?the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie= 1. chxf and chxie are in the timb channel x status and control register. 12.7 low-power modes the wait and stop instructions puts the mcu in low-power- consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 208 timer interface module b (timb) motorola 12.7.1 wait mode the timb remains active after the execution of a wait instruction. in wait mode the timb registers are not accessible by the cpu. any enabled cpu interrupt request from the timb can bring the mcu out of wait mode. if timb functions are not required during wait mode, reduce power consumption by stopping the timb before executing the wait instruction. 12.7.2 stop mode the timb is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the timb counter. timb operation resumes when the mcu exit stop mode after an external interrupt. 12.8 timb during break interrupts a break interrupt stops the timb counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 8.8.3 sim break flag control register . to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o signals MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 209 12.9 i/o signals port f shares four pins with the timb and port d shares one. ptd4/tbclk is an external clock input to the timb prescaler. the four timb channel i/o pins are ptf4/tbch0, ptf5/tbch1, ptf2/tbch2, and ptf3/tbch3. 12.9.1 timb clock pin ptd4/tbclk is an external clock input that can be the clock source for the timb counter instead of the prescaled internal bus clock. select the ptd4/tbclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. see 12.10.1 timb status and control register . the minimum tbclk pulse width, tbclk lmin or tbclk hmin , is: the maximum tbclk frequency is: bus frequency ? 2 ptd4/tbclk is available as a general-purpose i/o pin when not used as the timb clock input. when the ptd4/tbclk pin is the timb clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 12.9.2 timb channel i/o pins each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptf2/tbch2 and ptf5/tbch1 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------------------------- t su + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 210 timer interface module b (timb) motorola 12.10 i/o registers the following i/o registers control and monitor operation of the timb: timb status and control register (tbsc) timb counter registers (tbcnth:tbcntl) timb counter modulo registers (tbmodh:tbmodl) timb channel status and control registers (tbsc0, tbsc1, tbsc2, and tbsc3) timb channel registers (tbch0h:tbch0l, tbch1h:tbch1l, tbch2h:tbch2l, and tbch3h:tbch3l) 12.10.1 timb status and control register the timb status and control register does the following: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock address: $0040 bit 7 654321 bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 12-4. timb status and control register (tbsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 211 tof ?timb overflow flag bit this read/write flag is set when the timb counter resets to $0000 after reaching the modulo value programmed in the timb counter modulo registers. clear tof by reading the timb status and control register when tof is set and then writing a logic zero to tof. if another timb overflow occurs before the clearing sequence is complete, then writing logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = timb counter has reached modulo value 0 = timb counter has not reached modulo value toie ?timb overflow interrupt enable bit this read/write bit enables timb overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled tstop ?timb stop bit this read/write bit stops the timb counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note: do not set the tstop bit before entering wait mode if the timb is required to exit wait mode. trst ?timb reset bit setting this write-only bit resets the timb counter and the timb prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the timb counter is reset and always reads as logic zero. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 212 timer interface module b (timb) motorola ps[2:0] ?prescaler select bits these read/write bits select either the ptd4/tbclk pin or one of the seven prescaler outputs as the input to the timb counter as table 12-2 shows. reset clears the ps[2:0] bits. 12.10.2 timb counter registers the two read-only timb counter registers contain the high and low bytes of the value in the timb counter. reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears the timb counter registers. note: if you read tbcnth during a break interrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. table 12-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock ? 1 0 0 1 internal bus clock ? 2 0 1 0 internal bus clock ? 4 0 1 1 internal bus clock ? 8 1 0 0 internal bus clock ? 16 1 0 1 internal bus clock ? 32 1 1 0 internal bus clock ? 64 1 1 1 ptd4/tbclk address: $0041 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 = unimplemented figure 12-5. timb counter register high (tbcnth) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 213 12.10.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the modulo value, the overflow flag (tof) becomes set, and the timb counter resumes counting from $0000 at the next clock. writing to the high byte (tbmodh) inhibits the tof bit and overflow interrupts until the low byte (tbmodl) is written. reset sets the timb counter modulo registers. note: reset the timb counter before writing to the timb counter modulo registers. address: $0042 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 = unimplemented figure 12-6. timb counter register low (tbcntl) address: $0043 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 figure 12-7. timb counter modulo register high (tbmodh) address: $0044 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 11111111 figure 12-8. timb counter modulo register low (tbmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 214 timer interface module b (timb) motorola 12.10.4 timb channel status and control registers each of the timb channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on timb overflow selects 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation address: $0045 bit 7 654321 bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 figure 12-9. timb channel 0 status and control register (tbsc0) address: $0048 bit 7 654321 bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 figure 12-10. timb channel 1 status and control register (tbsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 215 chxf ?channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the timb counter registers matches the value in the timb channel x registers. when tim cpu interrupt requests are enabled (chxie = 1), clear chxf by reading timb channel x status and control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ?channel x interrupt enable bit this read/write bit enables timb cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled address: $0032 bit 7 654321 bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 figure 12-11. timb channel 2 status and control register (tbsc2) address: $0035 bit 7 654321 bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 figure 12-12. timb channel 3 status and control register (tbsc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 216 timer interface module b (timb) motorola msxb ?mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the timb channel 0 and timb channel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ?mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 12-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tbchx pin. see table 12-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the timb status and control register (tbsc). elsxb and elsxa ?edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to the port i/o, and pin tbchx is available as a general-purpose i/o pin. table 12-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 217 note: before enabling a timb channel register for input capture operation, make sure that the tbchx pin is stable for at least two bus clocks. tovx ?toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggle on timb counter overflow. note: when tovx is set, a timb counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ?channel x maximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 12-13 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 12-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 218 timer interface module b (timb) motorola figure 12-13. chxmax latency 12.10.5 timb channel registers these read/write registers contain the captured timb counter value of the input capture function or the output compare value of the output compare function. the state of the timb channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures until the low byte (tbchxl) is read. in output compare mode (msxb:msxa 1 0:0), writing to the high byte of the timb channel x registers (tbchxh) inhibits output compares until the low byte (tbchxl) is written. output overflow tbchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare address: $0046 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-14. timb channel 0 register high (tbch0h) address: $0047 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 12-15. timb channel 0 register low (tbch0l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola timer interface module b (timb) 219 address: $0049 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-16. timb channel 1 register high (tbch1h) address: $004a bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 12-17. timb channel 1 register low (tbch1l) address: $0033 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-18. timb channel 2 register high (tbch2h) address: $0034 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 12-19. timb channel 2 register low (tbch2l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module b (timb) technical data MC68HC908AB32 ? rev. 1.0 220 timer interface module b (timb) motorola address: $0036 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-20. timb channel 3 register high (tbch3h) address: $0037 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 12-21. timb channel 3 register low (tbch3l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola programmable interrupt timer (pit) 221 technical data ?MC68HC908AB32 section 13. programmable interrupt timer (pit) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4.1 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.6 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.7.1 pit status and control register. . . . . . . . . . . . . . . . . . . . . 225 13.7.2 pit counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.7.3 pit counter modulo registers . . . . . . . . . . . . . . . . . . . . . . 228 13.2 introduction this section describes the programmable interrupt timer (pit), which is a timer whose counter is clocked internally via software programmable options. figure 13-1 is a block diagram of the pit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) technical data MC68HC908AB32 ? rev. 1.0 222 programmable interrupt timer (pit) motorola 13.3 features features of the pit include the following: programmable pit clock input free-running or modulo up-count operation pit counter stop and reset bits 13.4 functional description figure 13-1 shows the structure of the pit. the central component of the pit is the 16-bit pit counter that can operate as a free-running counter or a modulo up-counter. the counter provides the timing reference for the interrupt. the pit counter modulo registers, pmodh:pmodl, control the modulo value of the counter. software can read the counter value at any time without affecting the counting sequence. figure 13-1. pit block diagram prescaler prescaler select 16-bit comparator pps2 pps1 pps0 pof poie pmodh:pmodl prst pstop 16-bit counter internal interrupt logic bus clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola programmable interrupt timer (pit) 223 13.4.1 pit counter prescaler the clock source can be one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, pps[2:0] in the status and control register select the pit clock source. the value in the pit counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. the pit overflow flag (pof) is set when the pit counter value rolls over to $0000 after matching the value in the pit counter modulo registers. the pit interrupt enable bit, poie, enables pit overflow cpu interrupt requests. pof and poie are in the pit status and control register. addr. register name bit 7 654321 bit 0 $004b pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset: 00100000 $004c pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $004d pit counter register low (pcntl) read: bit 7 654321 bit 0 write: reset: 00000000 $004e pit counter modulo register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 $004f pit counter modulo register low (pmodl) read: bit 7 654321 bit 0 write: reset: 11111111 = unimplemented figure 13-2. pit i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) technical data MC68HC908AB32 ? rev. 1.0 224 programmable interrupt timer (pit) motorola 13.5 low-power modes the wait and stop instructions put the mcu in low-power- consumption standby modes. 13.5.1 wait mode the pit remains active after the execution of a wait instruction. in wait mode the pit registers are not accessible by the cpu. any enabled cpu interrupt request from the pit can bring the mcu out of wait mode. if pit functions are not required during wait mode, reduce power consumption by stopping the pit before executing the wait instruction. 13.5.2 stop mode the pit is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the pit counter. pit operation resumes when the mcu exits stop mode after an external interrupt. 13.6 pit during break interrupts a break interrupt stops the pit counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 8.8.3 sim break flag control register . to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola programmable interrupt timer (pit) 225 bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 13.7 i/o registers the following i/o registers control and monitor operation of the pit: pit status and control register (psc) pit counter registers (pcnth:pcntl) pit counter modulo registers (pmodh:pmodl) 13.7.1 pit status and control register the pit status and control register does the following: enables pit interrupt flags pit overflows stops the pit counter resets the pit counter prescales the pit counter clock address: $004b bit 7 654321 bit 0 read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset: 00100000 = unimplemented figure 13-3. pit status and control register (psc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) technical data MC68HC908AB32 ? rev. 1.0 226 programmable interrupt timer (pit) motorola pof ?pit overflow flag bit this read/write flag is set when the pit counter resets to $0000 after reaching the modulo value programmed in the pit counter modulo registers. clear pof by reading the pit status and control register when pof is set and then writing a logic zero to pof. if another pit overflow occurs before the clearing sequence is complete, then writing logic zero to pof has no effect. therefore, a pof interrupt request cannot be lost due to inadvertent clearing of pof. reset clears the pof bit. writing a logic one to pof has no effect. 1 = pit counter has reached modulo value 0 = pit counter has not reached modulo value poie ?pit overflow interrupt enable bit this read/write bit enables pit overflow interrupts when the pof bit becomes set. reset clears the poie bit. 1 = pit overflow interrupts enabled 0 = pit overflow interrupts disabled pstop ?pit stop bit this read/write bit stops the pit counter. counting resumes when pstop is cleared. reset sets the pstop bit, stopping the pit counter until software clears the pstop bit. 1 = pit counter stopped 0 = pit counter active note: do not set the pstop bit before entering wait mode if the pit is required to exit wait mode. prst ?pit reset bit setting this write-only bit resets the pit counter and the pit prescaler. setting prst has no effect on any other registers. counting resumes from $0000. prst is cleared automatically after the pit counter is reset and always reads as logic zero. reset clears the prst bit. 1 = prescaler and pit counter cleared 0 = no effect note: setting the pstop and prst bits simultaneously stops the pit counter at a value of $0000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola programmable interrupt timer (pit) 227 pps[2:0] ?pit prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the pit counter as table 13-1 shows. reset clears the pps[2:0] bits. 13.7.2 pit counter registers the two read-only pit counter registers contain the high and low bytes of the value in the pit counter. reading the high byte (pcnth) latches the contents of the low byte (pcntl) into a buffer. subsequent reads of pcnth do not affect the latched pcntl value until pcntl is read. reset clears the pit counter registers. setting the pit reset bit (prst) also clears the pit counter registers. note: if you read pcnth during a break interrupt, be sure to unlatch pcntl by reading pcntl before exiting the break interrupt. otherwise, pcntl retains the value latched during the break. table 13-1. pit prescaler selection pps2 pps1 pps0 pit clock source 0 0 0 internal bus clock ? 1 0 0 1 internal bus clock ? 2 0 1 0 internal bus clock ? 4 0 1 1 internal bus clock ? 8 1 0 0 internal bus clock ? 16 1 0 1 internal bus clock ? 32 1 1 0 internal bus clock ? 64 1 1 1 internal bus clock ? 64 address: $004c bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 = unimplemented figure 13-4. pit counter register high (pcnth) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer (pit) technical data MC68HC908AB32 ? rev. 1.0 228 programmable interrupt timer (pit) motorola 13.7.3 pit counter modulo registers the read/write pit modulo registers contain the modulo value for the pit counter. when the pit counter reaches the modulo value, the overflow flag (pof) becomes set, and the pit counter resumes counting from $0000 at the next clock. writing to the high byte (pmodh) inhibits the pof bit and overflow interrupts until the low byte (pmodl) is written. reset sets the pit counter modulo registers. note: reset the pit counter before writing to the pit counter modulo registers. address: $004d bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 = unimplemented figure 13-5. pit counter register low (pcntl) address: $004e bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 figure 13-6. pit counter modulo register high (pmodh) address: $004f bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 11111111 figure 13-7. pit counter modulo register low (pmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola analog-to-digital converter (adc) 229 technical data ?MC68HC908AB32 section 14. analog-to-digital converter (adc) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.7.1 adc analog power pin (v ddaref ). . . . . . . . . . . . . . . . . . . 234 14.7.2 adc analog ground pin (a vss /v refl ) . . . . . . . . . . . . . . . 234 14.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 234 14.7.4 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8.1 adc status and control register (adscr). . . . . . . . . . . . 235 14.8.2 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . 237 14.8.3 adc clock register (adclk) . . . . . . . . . . . . . . . . . . . . . . 237 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data MC68HC908AB32 ? rev. 1.0 230 analog-to-digital converter (adc) motorola 14.2 introduction this section describes the 8-bit analog-to-digital converter (adc). 14.3 features features of the adc module include: eight channels with multiplexed input linear successive approximation with monotonicity 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock addr. register name bit 7 654321 bit 0 $0038 adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset: 00011111 $0039 adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: 00000000 $003a adc clock register (adclk) read: adiv2 adiv1 adiv0 adiclk 0000 write: reset: 00000000 = unimplemented figure 14-1. adc register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola analog-to-digital converter (adc) 231 14.4 functional description the adc provides eight pins for sampling external sources at pins ptb7/atd7?tb0/atd0. an analog multiplexer allows the single adc converter to select one of eight adc channels as adc voltage in (v adin ). v adin is converted by the successive approximation register-based analog-to-digital converter. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. (see figure 14-2 .) figure 14-2. adc block diagram internal data b u s read ddrbx write ddrbx reset write ptbx read ptbx ptbx ddrbx ptbx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock adch[4:0] adc data register aien coco disable disable adc channel x adiv[2:0] adiclk voltage in adc i/p channels f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data MC68HC908AB32 ? rev. 1.0 232 analog-to-digital converter (adc) motorola 14.4.1 adc port i/o pins ptb7/atd7?tb0/atd0 are general-purpose i/o (input/output) pins that share with the adc channels. the channel select bits define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin in use by the adc will return a logic 0. 14.4.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $ff (full scale). if the input voltage equals v refl , the adc converts it to $00. input voltages between v refh and v refl are a straight-line linear conversion. 14.4.3 conversion time conversion starts after a write to the adscr. one conversion will take between 16 and 17 adc clock cycles. the adivx and adiclk bits should be set to provide a 1-mhz adc clock frequency. 14.4.4 conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after the first conversion and will stay set until the next write of the adc status and control register or the next read of the adc data register. in single conversion mode, conversion begins with a write to the adscr. only one conversion occurs between writes to the adscr. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time bus frequency f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) interrupts MC68HC908AB32 ? rev. 1.0 technical data motorola analog-to-digital converter (adc) 233 14.4.5 accuracy and precision the conversion process is monotonic and has no missing codes. 14.5 interrupts when the aien bit is set, the adc module is capable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 14.6 low-power modes the wait and stop instruction can put the mcu in low power- consumption standby modes. 14.6.1 wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch[4:0] bits in the adc status and control register before executing the wait instruction. 14.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabilize the analog circuitry. 14.7 i/o signals the adc module has eight pins shared with port b, ptb7/atd7?tb0/atd0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data MC68HC908AB32 ? rev. 1.0 234 analog-to-digital converter (adc) motorola 14.7.1 adc analog power pin (v ddaref ) the adc analog portion uses v ddaref as its power pin. connect the v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddaref for good results. note: for maximum noise immunity, route v ddaref carefully and place bypass capacitors as close as possible to the package. 14.7.2 adc analog ground pin (a vss /v refl ) the adc analog portion uses a vss /v refl as its ground pin. connect the a vss /v refl pin to the same voltage potential as v ss . note: route a vss /v refl cleanly to avoid any offset errors. 14.7.3 adc voltage reference high pin (v refh ) v refh is the reference voltage for the adc. 14.7.4 adc voltage in (v adin ) v adin is the input voltage signal from one of the eight adc channels to the adc module. 14.8 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola analog-to-digital converter (adc) 235 14.8.1 adc status and control register (adscr) function of the adc status and control register is described here. coco ?conversions complete when the aien bit is a logic 0, the coco is a read-only bit which is set each time a conversion is completed except in the continuous conversion mode where it is set after the first conversion. this bit is cleared whenever the adscr is written or whenever the adr is read. if the aien bit is a logic 1, the coco becomes a read/write bit, which should be cleared to logic 0 for cpu to service the adc interrupt request. reset clears the coco bit. 1 = conversion completed (aien=0) 0 = conversion not completed (aien=0)/cpu interrupt (aien=1) aien ?adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written.reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ?adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion address: $0038 bit 7 654321 bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset: 00011111 figure 14-3. adc status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data MC68HC908AB32 ? rev. 1.0 236 analog-to-digital converter (adc) motorola adch[4:0] ?adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the eight adc channels, atd7?td0. the channels are detailed in table 14-1 . care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not being used. note: recovery from the disabled state requires one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes, as specified in table 14-1 , are used to verify the operation of the adc converter both in production test and for user applications. table 14-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 reserved 11100 11101 v refh 11110 v refl 11111 adc power off note: if any unused channels are selected, the resulting adc conversion will be unknown or reserved. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola analog-to-digital converter (adc) 237 14.8.2 adc data register (adr) one 8-bit result register, adc data register (adr), is provided. this register is updated each time an adc conversion completes. 14.8.3 adc clock register (adclk) the adc clock register (adclk) selects the clock frequency for the adc. adiv[2:0] ?adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 14-2 shows the available clock configurations. the adc clock should be set to approximately 1 mhz. address: $0039 bit 7 654321 bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: 00000000 = unimplemented figure 14-4. adc data register (adr) address: $003a bit 7 654321 bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: reset: 00000000 = unimplemented figure 14-5. adc clock register (adclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data MC68HC908AB32 ? rev. 1.0 238 analog-to-digital converter (adc) motorola adiclk ?adc input clock select bit adiclk selects either the bus clock or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. 1 = internal bus clock 0 = external clock (cgmxclk) table 14-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock ? 1 0 0 1 adc input clock ? 2 0 1 0 adc input clock ? 4 0 1 1 adc input clock ? 8 1 x x adc input clock ? 16 x = don? care adc input clock frequency adiv [2:0] ----------------------------------------------------------------------- 1mhz = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 239 technical data ?MC68HC908AB32 section 15. serial communications interface module (sci) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.5 inversion of transmitted output. . . . . . . . . . . . . . . . . . . 249 15.5.2.6 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 249 15.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 15.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . 260 15.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 260 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 240 serial communications interface module (sci) motorola 15.8.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.9.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 15.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 15.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.2 introduction this section describes the serial communications interface (sci) module, which allows high-speed asynchronous communications with peripheral devices and other mcus. note: references to dma (direct-memory access) and associated functions are only valid if the mcu has a dma module. this mcu does not have the dma function. any dma-related register bits should be left in their reset state for normal mcu operation. 15.3 features features of the sci module include the following: full-duplex operation standard mark/space non-return-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) features MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 241 two receiver wakeup methods: idle line wakeup address mark wakeup interrupt-driven operation with eight interrupt flags: transmitter empty transmission complete receiver full idle receiver input receiver overrun noise error framing error parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 242 serial communications interface module (sci) motorola 15.4 pin name conventions the generic names of the sci i/o pins are: rxd (receive data) txd (transmit data) sci i/o (input/output) lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 15-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in the text of this section. 15.5 functional description figure 15-1 shows the structure of the sci module. the sci allows full- duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. table 15-1. pin name conventions generic pin names: rxd txd full pin names: pte1/rxd pte0/txd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 243 figure 15-1. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 r orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control r ensci loops ensci pte1/rxd pte0/txd internal bus txinv loops ? 4 ? 16 pre- scaler baud divider cgmxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 244 serial communications interface module (sci) motorola addr. register name bit 7 654321 bit 0 $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 $0015 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset: u u 000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 11000000 $0017 sci status register 2 (scs2) read: bkf rpf write: reset: 00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 = unimplemented r = reserved u = unaffected figure 15-2. sci i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 245 15.5.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 15-3 . figure 15-3. sci data formats 15.5.2 transmitter figure 15-4 shows the structure of the sci transmitter. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 246 serial communications interface module (sci) motorola figure 15-4. sci transmitter r scte pen pty h876543210l 11-bit transmit stop start t8 r scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register r tc sctie tcie scte transmitter cpu interr upt request transmitter dma service request m ensci loops te pte0/txd txinv internal bus ? 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider ? 16 sctie cgmxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 247 15.5.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 15.5.2.2 character transmission during an sci transmission, the transmit shift register shifts a character out to the pte0/txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logic 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a logic 1 to the transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte0/txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 248 serial communications interface module (sci) motorola 15.5.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 15.5.2.4 idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the pte0/txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 249 note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just before writing the next byte to the scdr. 15.5.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 15.9.1 sci control register 1 .) 15.5.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ?the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ?the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 250 serial communications interface module (sci) motorola 15.5.3 receiver figure 15-5 shows the structure of the sci receiver. 15.5.3.1 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 15.5.3.2 character reception during an sci reception, the receive shift register shifts characters in from the pte1/rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 251 figure 15-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery r scrf or orie nf neie fe feie pe peie r scrie scrf ilie idle wakeup logic parity checking msb error cpu inte rrupt request dma service request cpu interrupt request sci data register r8 r orie neie feie peie scrie ilie rwu scrf idle or nf fe pe pte1/rxd internal bus pre- scaler baud divider ? 4 ? 16 scp1 scp0 scr2 scr1 scr0 scrie r cgmxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 252 serial communications interface module (sci) motorola 15.5.3.3 data sampling the receiver samples the pte1/rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 15-6 ): after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 15-6. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 253 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 15-2 summarizes the results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are logic 1s. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 15-3 summarizes the results of the data bit samples. table 15-2. start bit veri?ation rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 15-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 254 serial communications interface module (sci) motorola note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 15-4 summarizes the results of the stop bit samples. 15.5.3.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at the same time that the scrf bit is set. 15.5.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate table 15-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 255 tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 15-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 15-7. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 15-7 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 154 ------------------------- - 100 4.54% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 256 serial communications interface module (sci) motorola with the misaligned character shown in figure 15-7 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is fast data tolerance figure 15-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 15-8. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 15-8 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 170 163 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 154 ------------------------- - 100 3.90% ? = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 257 for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 15-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 15.5.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the pte1/rxd pin can bring the receiver out of the standby state: address mark ?an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ?when the wake bit is clear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the 170 176 170 ------------------------- - 100 3.53% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 258 serial communications interface module (sci) motorola sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 15.5.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ?the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ?the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the pte1/rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 15.5.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ?the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ?the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) low-power modes MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 259 framing error (fe) ?the fe bit in scs1 is set when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ?the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate sci error cpu interrupt requests. 15.6 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 15.6.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. refer to 8.7 low-power modes for information on exiting wait mode. 15.6.2 stop mode the sci module is inactive after the execution of a stop instruction, and thus the sci cannot cause an interrupt to exit stop mode. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. refer to 8.7 low-power modes for information on exiting stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 260 serial communications interface module (sci) motorola 15.7 sci during break module interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 15.8 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: pte0/txd ?transmit data pte1/rxd ?receive data 15.8.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from the sci transmitter. the sci shares the pte0/txd pin with port e. when the sci is enabled, the pte0/txd pin is an output regardless of the state of the ddre2 bit in data direction register e (ddre). 15.8.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when the sci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 261 15.9 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 15.9.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 262 serial communications interface module (sci) motorola loops ?loop mode select bit this read/write bit enables loop mode operation. in loop mode the pte1/rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ?enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ?transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, including idle, break, start, and stop bits. address: $0013 bit 7 654321 bit 0 read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 figure 15-9. sci control register 1 (scc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 263 m ?mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. (see table 15-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ?wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the pte1/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ?idle line type bit this read/write bit determines when the sci starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ?parity enable bit this read/write bit enables the sci parity function. (see table 15-5 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 15-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 264 serial communications interface module (sci) motorola pty ?parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. (see table 15-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 15.9.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: enables the scte bit to generate transmitter cpu interrupt requests enables the tc bit to generate transmitter cpu interrupt requests enables the scrf bit to generate receiver cpu interrupt requests enables the idle bit to generate receiver cpu interrupt requests table 15-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 265 enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ?sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ?transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ?sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ?idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0014 bit 7 654321 bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 figure 15-10. sci control register 2 (scc2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 266 serial communications interface module (sci) motorola te ?transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pte0/txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the pte0/txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ?receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ?receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 267 sbk ?send break bit setting and then clearing this read/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note: do not toggle the sbk bit immediately after setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. 15.9.3 sci control register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables these interrupts: receiver overrun interrupts noise error interrupts framing error interrupts parity error interrupts address: $0015 bit 7 654321 bit 0 read: r8 t8 r r orie neie feie peie write: reset: u u 000000 = unimplemented r = reserved u = unaffected figure 15-11. sci control register 3 (scc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 268 serial communications interface module (sci) motorola r8 ?received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ?transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. orie ?receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt requests from or bit disabled neie ?receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ?receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ?receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. (see 15.9.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 269 15.9.4 sci status register 1 sci status register 1 (scs1) contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ?sci transmitter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $0016 bit 7 654321 bit 0 read: scte tc scrf idle or nf fe pe write: reset: 11000000 = unimplemented figure 15-12. sci status register 1 (scs1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 270 serial communications interface module (sci) motorola tc ?transmission complete bit this read-only bit is set when the scte bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ?sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ?receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) or ?receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 271 bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 15-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag- clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag- clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ?receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the pte1/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ?receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 272 serial communications interface module (sci) motorola figure 15-13. flag clearing sequence pe ?receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 273 15.9.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ?break flag bit this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the pte1/rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ?reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7 654321 bit 0 read: bkf rpf write: reset: 00000000 = unimplemented figure 15-14. sci status register 2 (scs2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 274 serial communications interface module (sci) motorola 15.9.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?0/t0 ?receive/transmit data bits reading address $0018 accesses the read-only received data bits, r7:r0. writing to address $0018 writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. note: do not use read/modify/write instructions on the sci data register. address: $0018 bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 15-15. sci data register (scdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 275 15.9.7 sci baud rate register the baud rate register (scbr) selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ?sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 15-6 . reset clears scp1 and scp0. scr2?cr0 ?sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 15-7 . reset clears scr2?cr0. address: $0019 bit 7 654321 bit 0 read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 = unimplemented r = reserved figure 15-16. sci baud rate register (scbr) table 15-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 276 serial communications interface module (sci) motorola use this formula to calculate the sci baud rate: where: sci clock source = cgmxclk (see 9.5.6 crystal output frequency signal (cgmxclk) .) pd = prescaler divisor bd = baud rate divisor this makes the formula: table 15-8 shows the sci baud rates that can be generated with a 4.9152mhz cgmxclk. table 15-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 64 pd bd -------------------------------------------- - = baud rate cgmxclk 64 pd bd ------------------------------------ = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial communications interface module (sci) 277 table 15-8. sci baud rate selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (cgmxclk=4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface technical data MC68HC908AB32 ? rev. 1.0 278 serial communications interface module (sci) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 279 technical data ?MC68HC908AB32 section 16. serial peripheral interface module (spi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.4 pin name conventions and i/o register addresses . . . . . . . 281 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 16.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 16.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 285 16.6.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . 286 16.6.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . 288 16.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 289 16.7 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 16.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 301 16.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 301 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 280 serial peripheral interface module (spi) motorola 16.13.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.5 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . . 306 16.14.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 16.2 introduction this section describes the serial peripheral interface (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 16.3 features features of the spi module include the following: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency ? 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts: sprf (spi receiver full) spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode ? 2 c (inter-integrated circuit) compatibility i/o (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) pin name conventions and i/o register addresses MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 281 16.4 pin name conventions and i/o register addresses the text that follows describes the spi. the spi i/o pin names are ss (slave select), spsck (spi serial clock), cgnd (clock ground), mosi (master out slave in), and miso (master in/slave out). the spi shares four i/o pins with four parallel i/o ports. the full names of the spi i/o pins are shown in table 16-1 . the generic pin names appear in the text that follows. 16.5 functional description figure 16-1 summarizes the spi i/o registers and figure 16-2 shows the structure of the spi module. table 16-1. pin name conventions spi generic pin names: miso mosi ss spsck cgnd full spi pin names: spi pte5/miso pte6/mosi pte4/ss pte7/spsck v ss addr. register name bit 7 654321 bit 0 $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 00001000 $0012 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset = unimplemented r = reserved figure 16-1. spi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 282 serial peripheral interface module (spi) motorola figure 16-2. spi module block diagram the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt- driven. the following paragraphs describe the operation of the spi module. transmitter cpu interrupt request reserved receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout ? 2 clock select ? 2 clock divider ? 8 ? 32 ? 128 clock logic cpha cpol spi sprie r spe spwom sprf spte ovrf reserved m s pin control logic receive data register sptie spe internal bus from sim modfen errie control modf spmstr mosi miso spsck ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 283 16.5.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note: configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. (see 16.14.1 spi control register .) only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. (see figure 16-3 .) figure 16-3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 284 serial peripheral interface module (spi) motorola the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 16.14.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master? miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register clears the spte bit. 16.5.2 slave mode the spi operates in slave mode when the spmstr bit is clear. in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low until the transmission is complete. (see 16.8.2 mode fault error .) in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock that can be generated). the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 285 when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 16.6 transmission formats .) note: spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 16.6 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple- master bus contention. 16.6.1 clock phase and polarity controls software can select any of four combinations of serial clock (spsck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 286 serial peripheral interface module (spi) motorola the clock phase (cpha) control bit selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note: before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 16.6.2 transmission format when cpha = 0 figure 16-4 shows an spi transmission in which cpha is logic 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 16.8.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave? ss pin must be toggled back to high and then low again between each byte transmitted as shown in figure 16-5 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 287 figure 16-4. transmission format (cpha = 0) figure 16-5. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 288 serial peripheral interface module (spi) motorola 16.6.3 transmission format when cpha = 1 figure 16-6 shows an spi transmission in which cpha is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 16.8.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 16-6. transmission format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 289 when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 16.6.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr starts a transmission. cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 16-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 16-7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 290 serial peripheral interface module (spi) motorola figure 16-7. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock ? 2; earliest latest 2 possible start points spsck = internal clock ? 8; 8 possible start points earliest latest spsck = internal clock ? 32; 32 possible start points earliest latest spsck = internal clock ? 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? initiation delay from write spdr to transfer begin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) queuing transmission data MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 291 16.7 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit data register only when the spte bit is high. figure 16-8 shows the timing associated with doing back-to-back transmissions with the spi (spsck has cpha: cpol = 1:0). figure 16-8. sprf/spte cpu interrupt timing the transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 292 serial peripheral interface module (spi) motorola for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. 16.8 error conditions the following flags signal spi error conditions: overflow (ovrf) ?failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (modf) ?the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 16.8.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7. (see figure 16-4 and figure 16-6 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 293 interrupts share the same cpu interrupt vector. (see figure 16-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 16-9 shows how it is possible to miss an overflow. the first part of figure 16-9 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit can be set in between the time that spscr and spdr are read. figure 16-9. missed read of overflow condition in this case, an overflow can be missed easily. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 16-10 illustrates this process. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 294 serial peripheral interface module (spi) motorola figure 16-10. clearing sprf when ovrf interrupt is not enabled 16.8.2 mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects slave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 295 modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 16-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shift of the last data bit. (see 16.6 transmission formats .) note: setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 296 serial peripheral interface module (spi) motorola slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 16.9 interrupts four spi status flags can be enabled to generate cpu interrupt requests. table 16-2. spi interrupts flag request spte transmitter empty spi tr ansmitter cpu interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (sprie = 1) ovrf over?w spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) interrupts MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 297 reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt requests, regardless of the state of the spe bit. (see figure 16-11 .) the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. figure 16-11. spi interrupt request generation spte sptie sprf sprie r errie modf ovrf spe cpu interrupt request cpu interrupt request not available spi transmitter not available spi receiver/error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 298 serial peripheral interface module (spi) motorola the following sources in the spi status and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ?the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error cpu interrupt request. spi transmitter empty (spte) ?the spte bit becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. 16.10 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaulted back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr register (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to set all control bits again when spe is set back high for the next transmission. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) low-power modes MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 299 by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that was configured as a master with the modfen bit set. 16.11 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 16.11.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occurs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). (see 16.9 interrupts .) 16.11.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 300 serial peripheral interface module (spi) motorola 16.12 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. (see section 8. system integration module (sim) .) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 16.13 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. they are: miso ?data received mosi ?data transmitted spsck ?serial clock ?s ?slave select cgnd ?clock ground (internally connected to v ss ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o signals MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 301 the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 16.13.1 miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple- slave system, a logic 1 on the ss pin puts the miso pin in a high- impedance state. when enabled, the spi controls data direction of the miso pin regardless of the state of the data direction register of the shared i/o port. 16.13.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full- duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mosi pin regardless of the state of the data direction register of the shared i/o port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 302 serial peripheral interface module (spi) motorola 16.13.3 spsck (serial clock) the serial clock synchronizes data transmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 16.13.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 16.6 transmission formats .) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 16-12 . figure 16-12. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 16.14.2 spi status and control register .) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high- impedance state. the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o signals MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 303 when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. (see 16.8.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. (see table 16-3 .) 16.13.5 cgnd (clock ground) cgnd is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. it is internally connected to v ss as shown in table 16-1 . table 16-3. spi con?uration spe spmstr modfen spi configuration state of ss logic 0 x (1) x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi note 1. x = don? care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 304 serial peripheral interface module (spi) motorola 16.14 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) 16.14.1 spi control register the spi control register: enables spi module interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ?spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled address: $0010 bit 7 654321 bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 00101000 = unimplemented r = reserved figure 16-13. spi control register (spcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 305 spmstr ?spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ?clock polarity bit this read/write bit determines the logic state of the spsck pin between transmissions. (see figure 16-4 and figure 16-6 .) to transmit data between spi modules, the spi modules must have identical cpol values. reset clears the cpol bit. cpha ?clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 16-4 and figure 16-6 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 16-12 .) reset sets the cpha bit. spwom ?spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsck, mosi, and miso pins spe ?spi enable this read/write bit enables the spi module. clearing spe causes a partial reset of the spi. (see 16.10 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie?spi transmit interrupt enable this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 306 serial peripheral interface module (spi) motorola 16.14.2 spi status and control register the spi status and control register contains flags to signal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also contains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ?spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full address: $0011 bit 7 654321 bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 00001000 = unimplemented figure 16-14. spi status and control register (spscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 307 errie ?error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ?overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ?mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bit by reading the spi status and control register (spscr) with modf set and then writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ?spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note: do not write to the spi data register unless the spte bit is high. during an spte cpu interrupt, the cpu clears the spte bit by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 308 serial peripheral interface module (spi) motorola modfen ?mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not available as a general- purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardless of the value of modfen. (see 16.13.4 ss (slave select) .) if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 16.8.2 mode fault error .) spr1 and spr0 ?spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 16-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 16-4. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers MC68HC908AB32 ? rev. 1.0 technical data motorola serial peripheral interface module (spi) 309 16.14.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can contain different values. (see figure 16-2 .) r7?0/t7?0 ?receive/transmit data bits note: do not use read-modify-write instructions on the spi data register since the register read is not the same as the register written. address: $0012 bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 16-15. spi data register (spdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) technical data MC68HC908AB32 ? rev. 1.0 310 serial peripheral interface module (spi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 311 technical data ?MC68HC908AB32 section 17. input/output (i/o) ports 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 316 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 319 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 321 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 324 17.6.3 port d input pullup enable register (ptdpue). . . . . . . . . 325 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . 328 17.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.1 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.2 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . 330 17.8.3 port f input pullup enable register (ptfpue) . . . . . . . . . 332 17.9 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.1 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.2 data direction register g (ddrg) . . . . . . . . . . . . . . . . . . 333 17.10 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.1 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.2 data direction register h (ddrh). . . . . . . . . . . . . . . . . . . 335 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 312 input/output (i/o) ports motorola 17.2 introduction fifty-one bidirectional input-output (i/o) pins form eight parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7 654321 bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 $0006 data direction register c (ddrc) read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 figure 17-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 313 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $000a port g data register (ptg) read: 00000 ptg2 ptg1 ptg0 write: reset: unaffected by reset $000b port h data register (pth) read: 000000 pth1 pth0 write: reset: unaffected by reset $000c data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 $000d data direction register f (ddrf) read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 00000000 $000e data direction register g (ddrg) read: 00000 ddrg2 ddrg1 ddrg0 write: reset: 00000000 $000f data direction register h (ddrh) read: 000000 ddrh1 ddrh0 write: reset: 00000000 $003d port d input pullup enable register (ptdpue) read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset: 00000000 $003e port f input pullup enable register (ptfpue) read: ptfpue7 ptfpue6 ptfpue5 ptfpue4 ptfpue3 ptfpue2 ptfpue1 ptfpue0 write: reset: 00000000 addr. register name bit 7 654321 bit 0 figure 17-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 314 input/output (i/o) ports motorola table 17-1. port control register bits summary (sheet 1 of 2) port bit ddr module control pin module register control bit a 0 ddra0 pta0 1 ddra1 pta1 2 ddra2 pta2 3 ddra3 pta3 4 ddra4 pta4 5 ddra5 pta5 6 ddra6 pta6 7 ddra7 pta7 b 0 ddrb0 adc adscr $0038 adch[4:0] ptb0/atd0 1 ddrb1 ptb1/atd1 2 ddrb2 ptb2/atd2 3 ddrb3 ptb3/atd3 4 ddrb4 ptb4/atd4 5 ddrb5 ptb5/atd5 6 ddrb6 ptb6/atd6 7 ddrb7 ptb7/atd7 c 0 ddrc0 ptc0 1 ddrc1 ptc1 2 ddrc2 ddrc $0006 mclken ptc2/mclk 3 ddrc3 ptc3 4 ddrc4 ptc4 5 ddrc5 ptc5 d 0 ddrd0 ptd0 1 ddrd1 ptd1 2 ddrd2 ptd2 3 ddrd3 ptd3 4 ddrd4 timb tbsc $0040 ps[2:0] ptd4/tbclk 5 ddrd5 ptd5 6 ddrd6 tima tasc $0020 ps[2:0] ptd6/taclk 7 ddrd7 ptd7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 315 e 0 ddre0 sci scc1 $0013 ensci pte0/txd 1 ddre1 pte1/rxd 2 ddre2 tima tasc0 $0026 els0b:els0a pte2/tach0 3 ddre3 tasc1 $0029 els1b:els1a pte3/tach1 4 ddre4 spi spcr $0010 spe, spmstr pte4/ss 5 ddre5 spe pte5/miso 6 ddre6 pte6/mosi 7 ddre7 pte7spsck f 0 ddrf0 tima tasc2 $002c els2b:els2a ptf0/tach2 1 ddrf1 tasc3 $002f els3b:els3a ptf1/tach3 2 ddrf2 timb tbsc2 $0032 els2b:els2a ptf2/tbch2 3 ddrf3 tbsc3 $0035 els3b:els3a ptf3/tbch3 4 ddrf4 tbsc0 $0045 els0b:els0a ptf4/tbch0 5 ddrf5 tbsc1 $0048 els1b:els1a ptf5/tbch1 6 ddrf6 ptf6 7 ddrf7 ptf7 g 0 ddrg0 kbi kbier $0021 kbie0 ptg0/kbd0 1 ddrg1 kbie1 ptg1/kbd1 2 ddrg2 kbie2 ptg2/kbd2 h 0 ddrh0 kbie3 pth0/kbd3 1 ddrh1 kbie4 pth1/kbd4 table 17-1. port control register bits summary (sheet 2 of 2) port bit ddr module control pin module register control bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 316 input/output (i/o) ports motorola 17.3 port a port a is an 8-bit general-purpose bidirectional i/o port. 17.3.1 port a data register (pta) the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ?port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. 17.3.2 data direction register a (ddra) data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. address: $0000 bit 7 654321 bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 17-2. port a data register (pta) address: $0004 bit 7 654321 bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0000000 figure 17-3. data direction register a (ddra) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 317 ddra[7:0] ?data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 17-4 shows the port a i/o logic. figure 17-4. port a i/o circuit when ddrax is a logic 1, reading address $0000 reads the ptax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-2 summarizes the operation of the port a pins. table 17-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) notes : 1. x = don? care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 318 input/output (i/o) ports motorola 17.4 port b port b is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital converter (adc) module (see section 14. analog-to-digital converter (adc) ). 17.4.1 port b data register (ptb) the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ?port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. atd[7:0] ?adc channels atd[7:0] are pins used for the input channels to the analog-to-digital converter module. the channel select bits in the adc status and control register define which port b pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. note: care must be taken when reading port b while applying analog voltages to atd[7:0] pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptbx/atdx pin, while ptb is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. address: $0001 bit 7 654321 bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: atd7 atd6 atd5 atd4 atd3 atd2 atd2 atd0 figure 17-5. port b data register (ptb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 319 17.4.2 data direction register b (ddrb) data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb[7:0] ?data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 17-7 shows the port b i/o logic. figure 17-7. port b i/o circuit address: $0005 bit 7 654321 bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0000000 figure 17-6. data direction register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus to analog-to-digital converter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 320 input/output (i/o) ports motorola when ddrbx is a logic 1, reading address $0001 reads the ptbx data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-3 summarizes the operation of the port b pins. 17.5 port c port c is a 6-bit general-purpose bidirectional i/o port. ptc2 pin can be configured as an output pin for the system mclk clock. 17.5.1 port c data register (ptc) the port c data register contains a data latch for each of the six port c pins. table 17-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don? care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] address: $0002 bit 7 654321 bit 0 read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: mclk figure 17-8. port c data register (ptc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 321 ptc[5:0] ?port c data bits these read/write bits are software programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. mclk ?t12 system clock the system clock is driven out of the ptc2 pin when mclken is set. 17.5.2 data direction register c (ddrc) data direction register c determines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. mclken ?t12 system clock enable bit this read/write bit enables mclk to be an output signal on ptc2 pin. reset clears mclken. 1 = ptc2 pin configured as mclk output 0 = ptc2 pin configured as standard i/o pin ddrc[5:0] ?data direction register c bits these read/write bits control port c data direction. reset clears ddrc[5:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. figure 17-10 shows the port c i/o logic. address: $0006 bit 7 654321 bit 0 read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0000000 figure 17-9. data direction register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 322 input/output (i/o) ports motorola figure 17-10. port c i/o circuit when ddrcx is a logic 1, reading address $0002 reads the ptcx data latch. when ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-4 summarizes the operation of the port c pins. table 17-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 2 input, hi-z ddrc7 pin ptc2 1 2 output ddrc7 0 0x (1) notes : 1. x = don? care; except ptc2. input, hi-z (2) 2. hi-z = high impedance. ddrc[5:0] pin ptc[5:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[5:0] ptc[5:0] ptc[5:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus mclk mclken ptc2 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 323 17.6 port d port d is an 8-bit special function port that shares two of its pins with the timer interface module (see section 11. timer interface module a (tima) and section 12. timer interface module b (timb) ). each port d pin has 15ma current drive (sink) and programmable pullup. 17.6.1 port d data register (ptd) the port d data register contains a data latch for each of the eight port d pins. ptd[7:0] ?port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. taclk ?timer a clock input the ptd6 pin becomes taclk, the timer a (tima) external clock input when the tima prescaler select bits, ps[2:0] = 111. see section 11. timer interface module a (tima) . tbclk ?timer b clock input the ptd4 pin becomes tbclk, the timer b (timb) external clock input when the timb prescaler select bits, ps[2:0] = 111. see section 12. timer interface module b (timb) . address: $0003 bit 7 654321 bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: taclk tbclk additional functions: 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink input pullup input pullup input pullup input pullup input pullup input pullup input pullup input pullup figure 17-11. port d data register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 324 input/output (i/o) ports motorola 17.6.2 data direction register d (ddrd) data direction register d determines whether each port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. ddrd[7:0] ?data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. figure 17-13 shows the port d i/o logic. figure 17-13. port d i/o circuit address: $0007 bit 7 654321 bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 0 0000000 figure 17-12. data direction register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus ptdpuex ptd6 to taclk of tima ptd4 to tbclk of timb v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 325 when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-5 summarizes the operation of the port d pins. 17.6.3 port d input pullup enable register (ptdpue) the port d input pullup enable register (ptdpue) controls the input pullup device for each of the eight port d pins. each bit is individually configurable and requires that the data direction register, ddrd, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit? ddrd is configured for output mode. ptdpue[7:0] ?port d input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port pin. 1 = corresponding port d pin configured to have internal pullup 0 = corresponding port d pin internal pullup disconnected table 17-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don? care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] address: $003d bit 7 654321 bit 0 read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset: 0 0000000 figure 17-14. port d input pullup enable register (ptdpue) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 326 input/output (i/o) ports motorola 17.7 port e port e is an 8-bit special function port that shares two of its pins with the timer interface module (tima), two of its pins with the serial communications interface module (sci) and four of its pins with the serial peripheral interface module (spi). 17.7.1 port e data register (pte) the port e data register contains a data latch for each of the eight port e pins. pte[7:0] ?port e data bits these read/write bits are software programmable. data direction of each port e pin is under the control of the corresponding bit in data direction register e. reset has no effect on port e data. spsck ?spi serial clock the pte7/spsck pin is the serial clock input of a spi slave module and serial clock output of a spi master modules. when the spe bit is clear, the pte7/spsck pin is available for general-purpose i/o. see 16.14.1 spi control register . mosi ?master out/slave in the pte6/mosi pin is the master out/slave in terminal of the spi module. when the spe bit is clear, the pte6/mosi pin is available for general-purpose i /o. see 16.14.1 spi control register . address: $0008 bit 7 654321 bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: spsck mosi miso ss tach1 tach0 rxd txd figure 17-15. port e data register (pte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 327 miso ?master in/slave out the pte5/miso pin is the master in/slave out terminal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pte5/miso pin is available for general-purpose i/o. see 16.14.1 spi control register . ss ?slave select the pte4/ss pin is the slave select input of the spi module. when the spe bit is clear, or when the spi master bit, spmstr, is set, the pte4/ss pin is available for general-purpose i/o. see 16.14.1 spi control register . when the spi is enabled as a slave, the ddre4 bit in data direction register e (ddre) has no effect on the pte4/ss pin. tach[1:0] ?timer a channel i/o bits the pte3/tach1?te2/tach0 pins are the tima input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the pte3/tach1?te2/tach0 pins are timer channel i/o pins or general-purpose i/o pins. see 11.10.4 tima channel status and control registers . rxd ?sci receive data input the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see 15.9.1 sci control register 1 . txd ?sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. see 15.9.1 sci control register 1 . note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the spi module, tima, and sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 17-6 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 328 input/output (i/o) ports motorola 17.7.2 data direction register e (ddre) data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[7:0] ?data direction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 17-17 shows the port e i/o logic. figure 17-17. port e i/o circuit address: $000c bit 7 654321 bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0000000 figure 17-16. data direction register e (ddre) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port f MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 329 when ddrex is a logic 1, reading address $0008 reads the ptex data latch. when ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operation of the port e pins. 17.8 port f port f is an 8-bit special function port that shares six of its pins with the timer interface modules (tima and timb). 17.8.1 port f data register (ptf) the port f data register contains a data latch for each of the eight port f pins. table 17-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) notes : 1. x = don? care. input, hi-z (2) 2. hi-z = high impedance. ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddre[7:0] pte[7:0] pte[7:0] address: $0009 bit 7 654321 bit 0 read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset alternative function: tbch1 tbch0 tbch3 tbch2 tach3 tach2 additional function: input pullup input pullup input pullup input pullup input pullup input pullup input pullup input pullup figure 17-18. port f data register (ptf) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 330 input/output (i/o) ports motorola ptf[7:0] ?port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the corresponding bit in data direction register f. reset has no effect on port f data. tach[3:2] and tbch[3:0] ?timer channel i/o bits the ptf5/tbch1?tf0/tach2 pins are the tima and timb input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf5/tbch1?tf0/tach2 pins are timer channel i/o pins or general-purpose i/o pins. see 11.10.4 tima channel status and control registers and 12.10.4 timb channel status and control registers . note: data direction register f (ddrf) does not affect the data direction of port f pins that are being used by tima and timb. however, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. see table 17-7 . 17.8.2 data direction register f (ddrf) data direction register f determines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a logic 0 disables the output buffer. ddrf[7:0] ?data direction register f bits these read/write bits control port f data direction. reset clears ddrf[7:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input address: $000d bit 7 654321 bit 0 read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 0 0000000 figure 17-19. data direction register f (ddrf) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port f MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 331 note: avoid glitches on port f pins by writing to the port f data register before changing data direction register f bits from 0 to 1. figure 17-20 shows the port f i/o logic. figure 17-20. port f i/o circuit when ddrfx is a logic 1, reading address $0009 reads the ptfx data latch. when ddrfx is a logic 0, reading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-7 summarizes the operation of the port f pins. table 17-7. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0x (1) notes : 1. x = don? care. input, hi-z (2) 2. hi-z = high impedance. ddrf[7:0] pin ptf[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrf[7:0] ptf[7:0] ptf[7:0] read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus ptf5 to tbch1, ptf4 to tbch0, ptf3 to tbch3, ptf2 to tbch2 of timb ptf1 to tach3, ptf0 to tach2 of tima ptfpuex v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 332 input/output (i/o) ports motorola 17.8.3 port f input pullup enable register (ptfpue) the port f input pullup enable register (ptfpue) controls the input pullup device for each of the eight port f pins. each bit is individually configurable and requires that the data direction register, ddrf, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit? ddrf is configured for output mode. ptfpue[7:0] ?port f input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port pin. 1 = corresponding port f pin configured to have internal pullup 0 = corresponding port f pin internal pullup disconnected 17.9 port g port g is a 3-bit special-function port that shares all three of its pins with the keyboard interrupt (kbi) module. 17.9.1 port g data register (ptg) the port g data register (ptg) contains a data latch for each of the three port g pins. address: $003e bit 7 654321 bit 0 read: ptfpue7 ptfpue6 ptfpue5 ptfpue4 ptfpue3 ptfpue2 ptfpue1 ptfpue0 write: reset: 0 0000000 figure 17-21. port f input pullup enable register (ptfpue) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port g MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 333 ptg[2:0] ?port g data bits these read/write bits are software programmable. data direction of each port g pin is under the control of the corresponding bit in data direction register g. reset has no effect on port g data. kbd[2:0] ?the keyboard interrupt enable bits, kbie[2:0], in the keyboard interrupt enable register (kbier), enable the port g pins as external interrupt pins. see section 19. keyboard interrupt module (kbi) . 17.9.2 data direction register g (ddrg) data direction register g determines whether each port g pin is an input or an output. writing logic 1 to a ddrg bit enables the output buffer for the corresponding port g pin; a logic 0 disables the output buffer. address: $000a bit 7 654321 bit 0 read: 00000 ptg2 ptg1 ptg0 write: reset: unaffected by reset alternative function: kbd2 kbd1 kbd0 figure 17-22. port g data register (ptg) address: $000e bit 7 654321 bit 0 read: 0 0000 ddrg2 ddrg1 ddrg0 write: reset: 0 0000000 figure 17-23. data direction register g (ddrg) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 334 input/output (i/o) ports motorola ddrg[2:0] ?data direction register g bits these read/write bits control port g data direction. reset clears ddrg[2:0], configuring all port g pins as inputs. 1 = corresponding port g pin configured as output 0 = corresponding port g pin configured as input note: avoid glitches on port g pins by writing to the port g data register before changing data direction register g bits from 0 to 1. figure 17-24 shows the port g i/o logic. figure 17-24. port g i/o circuit when ddrgx is a logic 1, reading address $000a reads the ptgx data latch. when ddrgx is a logic 0, reading address $000a reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operation of the port g pins. table 17-8. port g pin functions ddrg bit ptg bit i/o pin mode accesses to ddrg accesses to ptg read/write read write 0x (1) notes : 1. x = don? care. input, hi-z (2) 2. hi-z = high impedance. ddrg[2:0] pin ptg[2:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrg[2:0] ptg[2:0] ptg[2:0] read ddrg ($000e) write ddrg ($000e) reset write ptg ($000a) read ptg ($000a) ptgx ddrgx ptgx internal data bus kbi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port h MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 335 17.10 port h port h is a 2-bit special-function port that shares all two of its pins with the keyboard interrupt (kbi) module. 17.10.1 port h data register (pth) the port h data register (pth) contains a data latch for each of the two port h pins. pth[1:0] ?port h data bits these read/write bits are software programmable. data direction of each port h pin is under the control of the corresponding bit in data direction register h. reset has no effect on port h data. kbd[4:3] ?the keyboard interrupt enable bits, kbie[4:3], in the keyboard interrupt enable register (kbier), enable the port h pins as external interrupt pins. see section 19. keyboard interrupt module (kbi) . 17.10.2 data direction register h (ddrh) data direction register h determines whether each port h pin is an input or an output. writing logic 1 to a ddrh bit enables the output buffer for the corresponding port h pin; a logic 0 disables the output buffer. address: $000b bit 7 654321 bit 0 read: 000000 pth1 pth0 write: reset: unaffected by reset alternative function: kbd4 kbd3 figure 17-25. port h data register (pth) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 336 input/output (i/o) ports motorola ddrh[1:0] ?data direction register h bits these read/write bits control port h data direction. reset clears ddrh[1:0], configuring all port h pins as inputs. 1 = corresponding port h pin configured as output 0 = corresponding port h pin configured as input note: avoid glitches on port h pins by writing to the port h data register before changing data direction register h bits from 0 to 1. figure 17-27 shows the port h i/o logic. figure 17-27. port h i/o circuit when ddrhx is a logic 1, reading address $000b reads the pthx data latch. when ddrhx is a logic 0, reading address $000b reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operation of the port h pins. address: $000f bit 7 654321 bit 0 read: 0 00000 ddrh1 ddrh0 write: reset: 0 0000000 figure 17-26. data direction register h (ddrh) read ddrh ($000f) write ddrh ($000f) reset write pth ($000b) read pth ($000b) pthx ddrhx pthx internal data bus kbi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port h MC68HC908AB32 ? rev. 1.0 technical data motorola input/output (i/o) ports 337 table 17-9. port h pin functions ddrh bit pth bit i/o pin mode accesses to ddrh accesses to pth read/write read write 0x (1) input, hi-z (2) ddrh[1:0] pin pth[1:0] (3) 1 x output ddrh[1:0] pth[1:0] pth[1:0] notes : 1. x = don? care. 2. hi-z = high impedance. 3. writing affects data register, but does not affect the input. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data MC68HC908AB32 ? rev. 1.0 338 input/output (i/o) ports motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola external interrupt (irq) 339 technical data ?MC68HC908AB32 section 18. external interrupt (irq) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 18.5 irq status and control register (iscr) . . . . . . . . . . . . . . . . 343 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 344 18.2 introduction the irq (external interrupt) module provides a maskable interrupt input. 18.3 features features of the irq module include the following: a dedicated external interrupt pin, i rq irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908AB32 ? rev. 1.0 340 external interrupt (irq) motorola 18.4 functional description a logic 0 applied to the external interrupt pin can latch a cpu interrupt request. figure 18-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ?a vector fetch automatically generates an interrupt acknowledge signal that clears the irq latch. software clear ?software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack bit clears the irq latch. reset ?a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software- configurable to be either falling-edge or falling-edge and low-level- triggered. the mode bit in the iscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the iscr mask all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask bit is clear. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola external interrupt (irq) 341 note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. (see 8.6 exception control .) figure 18-1. irq module block diagram ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device irq addr. register name bit 7 654321 bit 0 $001a irq status and control register (iscr) read: 0000 irqf 0 imask mode write: ack reset: 00000000 = unimplemented figure 18-2. irq i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908AB32 ? rev. 1.0 342 external interrupt (irq) motorola 18.4.1 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ?a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ?as long as the irq pin is at logic 0, irq remains active. the vector fetch or software clear and the return of the irq pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq status and control register (iscr) MC68HC908AB32 ? rev. 1.0 technical data motorola external interrupt (irq) 343 18.5 irq status and control register (iscr) the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering sensitivity of the irq interrupt pin irqf ?irq flag this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ?irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ?irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ?irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001a bit 7 654321 bit 0 read: 0000 irqf 0 imask mode write: ack reset: 00000000 = unimplemented figure 18-3. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data MC68HC908AB32 ? rev. 1.0 344 external interrupt (irq) motorola 18.6 irq module during break interrupts the system integration module (sim) controls whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 8. system integration module (sim) .) to allow software to clear the irq latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 345 technical data ?MC68HC908AB32 section 19. keyboard interrupt module (kbi) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 19.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 19.5.2 keyboard status and control register. . . . . . . . . . . . . . . . 349 19.5.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 351 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 352 19.2 introduction the keyboard interrupt module (kbi) provides five independently maskable external interrupts which are accessible via ptg0?tg2 and pth0?th1 pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908AB32 ? rev. 1.0 346 keyboard interrupt module (kbi) motorola 19.3 features features of the keyboard interrupt module include the following: five keyboard interrupt pins with pullup devices separate keyboard interrupt enable bits and one keyboard interrupt mask built-in pull-up device if input pin is configured as input port bit programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes 19.4 i/o pins the five keyboard interrupt pins are shared with standard port i/o pins. the full name of the kbi pins are listed in table 19-1 . the generic pin name appear in the text that follows. addr. register name bit 7 654321 bit 0 $001b keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 $0021 keyboard interrupt enable register (kbier) read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 = unimplemented figure 19-1. kbi i/o register summary table 19-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbd0 ptg0/kbd0 kbie0 kbd1 ptg1/kbd1 kbie1 kbd2 ptg2/kbd2 kbie2 kbd3 pth0/kbd3 kbie3 kbd4 pth1/kbd4 kbie4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 347 19.5 functional description figure 19-2. keyboard interrupt block diagram writing to the kbie4?bie0 bits in the keyboard interrupt enable register independently enables or disables the corresponding port pin as a keyboard interrupt pin. enabling a keyboard interrupt pin also enables its internal pull-up device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: kbie0 kbie4 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbd4 kbd0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908AB32 ? rev. 1.0 348 keyboard interrupt module (kbi) motorola vector fetch or software clear ?a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register kbscr. the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffd2 and $ffd3. return of all enabled keyboard interrupt pins to logic 1 ?as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, disable the pull- up device, use the data direction register to configure the pin as an input and then read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 349 19.5.1 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddr bits in the data direction register. 2. write logic 1s to the appropriate port data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 19.5.2 keyboard status and control register flags keyboard interrupt requests. acknowledges keyboard interrupt requests. masks keyboard interrupt requests. controls keyboard interrupt triggering sensitivity. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908AB32 ? rev. 1.0 350 keyboard interrupt module (kbi) motorola bits 7? ?not used these read-only bits always read as logic 0s. keyf ?keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ?keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. reset clears ackk. imaskk?keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ?keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001b bit 7 654321 bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 = unimplemented figure 19-3. keyboard status and control register (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) wait mode MC68HC908AB32 ? rev. 1.0 technical data motorola keyboard interrupt module (kbi) 351 19.5.3 keyboard interrupt enable register the keyboard interrupt enable register enables or disables the corresponding port pin to operate as a keyboard interrupt pin. kbie4?bie0 ?keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbdx pin enabled as keyboard interrupt pin 0 = kbdx pin not enabled as keyboard interrupt pin 19.6 wait mode the keyboard modules remain active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 19.7 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. address: $0021 bit 7 654321 bit 0 read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: port pin: pth1/ kbd4 pth0/ kbd3 ptg2/ kbd2 ptg1/ kbd1 ptg0 /kbd0 reset: 00000000 figure 19-4. keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data MC68HC908AB32 ? rev. 1.0 352 keyboard interrupt module (kbi) motorola 19.8 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola computer operating properly (cop) 353 technical data ?MC68HC908AB32 section 20. computer operating properly (cop) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 356 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 358 20.2 introduction the computer operating properly (cop) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in configuration register 1 (config1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data MC68HC908AB32 ? rev. 1.0 354 computer operating properly (cop) motorola 20.3 functional description figure 20-1 shows the structure of the cop module. figure 20-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 cgmxclk cycle overflow option, a 4.9152mhz crystal gives a cop timeout period of 53.3ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. copctl write cgmxclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config1) cop rate sel (coprs from config1) clear stages 5?2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals MC68HC908AB32 ? rev. 1.0 technical data motorola computer operating properly (cop) 355 a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst during the break state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. 20.4 i/o signals the following paragraphs describe the signals shown in figure 20-1 . 20.4.1 cgmxclk cgmxclk is the crystal oscillator output signal. cgmxclk frequency is equal to the crystal frequency. 20.4.2 stop instruction the stop instruction clears the cop prescaler. 20.4.3 copctl write writing any value to the cop control register (copctl) (see 20.5 cop control register ) clears the cop counter and clears bits 12 through 5 of the prescaler. reading the cop control register returns the low byte of the reset vector. 20.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data MC68HC908AB32 ? rev. 1.0 356 computer operating properly (cop) motorola 20.4.5 internal reset an internal reset clears the cop prescaler and the cop counter. 20.4.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 20.4.7 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register 1. (see figure 20-2 .) 20.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1. (see figure 20-2 .) coprs ?cop rate select bit coprs selects the cop timeout period. reset clears coprs. 1 = cop timeout period is 2 18 ?2 4 cgmxclk cycles 0 = cop timeout period is 2 13 ?2 4 cgmxclk cycles copd ?cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7 654321 bit 0 read: lvistop r lvirstd lvipwrd ssrec coprs stop copd write: reset: 00000000 r = reserved figure 20-2. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register MC68HC908AB32 ? rev. 1.0 technical data motorola computer operating properly (cop) 357 20.5 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 20.6 interrupts the cop does not generate cpu interrupt requests. 20.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is entered by having blank reset vectors and not having v tst on the irq pin, the cop is automatically disabled until a por occurs. 20.8 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. address: $ffff bit 7 654321 bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 20-3. cop control register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data MC68HC908AB32 ? rev. 1.0 358 computer operating properly (cop) motorola 20.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 20.8.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction is disabled, execution of a stop instruction results in an illegal opcode reset. 20.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola low-voltage inhibit (lvi) 359 technical data ?MC68HC908AB32 section 21. low-voltage inhibit (lvi) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 21.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.5 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.2 introduction this section describes the low-voltage inhibit module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 21.3 features features of the lvi module include the following: programmable lvi reset programmable lvi module power programmable stop mode operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data MC68HC908AB32 ? rev. 1.0 360 low-voltage inhibit (lvi) motorola 21.4 functional description figure 21-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. the lvi power bit, lvipwrd, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, lvi tripf , and remains at or below that level for 9 or more consecutive cpu cycles. setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. lvistop, lvipwrd, and lvirstd are in the configuration register 1 (config1). see section 6. configuration register (config) for details of the lvi? configuration bits. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr , which causes the mcu to exit reset. see 8.4.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. note: where lvi trip falling voltage lvi tripf = v lvii and lvi trip rising voltage lvi tripr = v lvii + h lvi (see section 23. electrical specifications .) figure 21-1. lvi module block diagram low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvi trip = 0 v dd lvi trip = 1 from config1 from config1 v dd from config1 lvirstd to lvisr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola low-voltage inhibit (lvi) 361 21.4.1 polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bit. in configuration register 1, the lvipwrd bit must be at logic 0 to enable the lvi module, and the lvirstd bit must be at logic 1 to disable lvi resets. 21.4.2 forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the lvi tripf level and remains at or below that level for 9 or more consecutive cpu cycles. in configuration register 1, the lvipwrd and lvirstd bits must be at logic 0 to enable the lvi module and to enable lvi resets. 21.4.3 false reset protection the v dd pin level is digitally filtered to reduce false resets due to power supply noise. in order for the lvi module to reset the mcu, v dd must remain at or below the lvi tripf level for 9 or more consecutive cpu cycles. v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. address: $fe0f bit 7 654321 bit 0 read: lviout 0000000 write: reset: 00000000 = unimplemented figure 21-2. lvi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data MC68HC908AB32 ? rev. 1.0 362 low-voltage inhibit (lvi) motorola 21.5 lvi status register (lvisr) the lvi status register flags v dd voltages below the lvi tripf level . lviout ?lvi output bit this read-only flag becomes set when v dd falls below the lvi tripf voltage for 32 to 40 cgmxclk cycles. (see table 21-1 .) reset clears the lviout bit. 21.6 lvi interrupts the lvi module does not generate interrupt requests. address: $fe0f bit 7 654321 bit 0 read: lviout 0000000 write: reset: 00000000 = unimplemented figure 21-3. lvi status register (lvisr) table 21-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > lvi tripr any 0 v dd < lv i tripf < 32 cgmxclk cycles 0 v dd < lv i tripf 32 to 40 cgmxclk cycles 0 or 1 v dd < lv i tripf > 40 cgmxclk cycles 1 lv i tripf < v dd < lv i tripr any previous value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) low-power modes MC68HC908AB32 ? rev. 1.0 technical data motorola low-voltage inhibit (lvi) 363 21.7 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 21.7.1 wait mode if enabled, the lvi module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 21.7.2 stop mode if enabled in stop mode (lvistop set), the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) technical data MC68HC908AB32 ? rev. 1.0 364 low-voltage inhibit (lvi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola break module (brk) 365 technical data ?MC68HC908AB32 section 22. break module (brk) 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4.1 flag protection during break interrupts . . . . . . . . . . . . . . . 368 22.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 368 22.4.3 pit, tima, and timb during break interrupts . . . . . . . . . . 368 22.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 368 22.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 22.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 22.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 22.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 22.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 369 22.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 372 22.2 introduction this section describes the break module (brk). the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908AB32 ? rev. 1.0 366 break module (brk) motorola 22.3 features features of the break module include: accessible input/output (i/o) registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 22.4 functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu then loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 22-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) functional description MC68HC908AB32 ? rev. 1.0 technical data motorola break module (brk) 367 figure 22-1. break module block diagram iab15?ab8 iab7?ab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?ab0 break addr. register name bit 7 654321 bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 00000000 $fe03 sim break flag control register (sbfcr) read: bcfe rrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 $fe0d break address register low (brkl) read: bit 7 654321 bit 0 write: reset: 00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset: 00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 22-2. break module i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908AB32 ? rev. 1.0 368 break module (brk) motorola 22.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. 22.4.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 22.4.3 pit, tima, and timb during break interrupts a break interrupt stops all timer counters. 22.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 22.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 22.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set (see section 8. system integration module (sim) ). clear the sbsw bit by writing logic 0 to it. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers MC68HC908AB32 ? rev. 1.0 technical data motorola break module (brk) 369 22.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 22.6 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) 22.6.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ?break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7 654321 bit 0 read: brke brka 000000 write: reset: 00000000 = unimplemented figure 22-3. break status and control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908AB32 ? rev. 1.0 370 break module (brk) motorola brka ?break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) break address match 0 = (when read) no break address match 22.6.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 22.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. address: $fe0c bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 figure 22-4. break address register high (brkh) address: $fe0d bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 figure 22-5. break address register low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers MC68HC908AB32 ? rev. 1.0 technical data motorola break module (brk) 371 sbsw ?sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example. address: $fe00 bit 7 654321 bit 0 read: rrrrrr sbsw r write: note reset: 00000000 note: writing a logic 0 clears sbsw. r = reserved figure 22-6. sim break status register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) technical data MC68HC908AB32 ? rev. 1.0 372 break module (brk) motorola 22.6.4 sim break flag control register the sim break flag control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ?break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7 654321 bit 0 read: bcfe rrrrrrr write: reset: 0 r = reserved figure 22-7. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 373 technical data ?MC68HC908AB32 section 23. electrical specifications 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374 23.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 376 23.7 eeprom and memory characteristics . . . . . . . . . . . . . . . . . 377 23.8 5.0-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 378 23.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 23.11 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 23.12 clock generation module characteristics . . . . . . . . . . . . . . . 383 23.12.1 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 383 23.12.2 cgm component information . . . . . . . . . . . . . . . . . . . . . . 383 23.12.3 cgm acquisition/lock time information . . . . . . . . . . . . . . 384 23.13 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 385 23.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 374 electrical specifications motorola 23.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 23.6 5.0-v dc electrical characteristics for guaranteed operating conditions . note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) notes : 1. voltages referenced to v ss symbol value unit supply voltage v dd 0.3 to + 6.0 v input voltage v in v ss ?0.3 to v dd + 0.3 v maximum current per pin excluding v dd , v ss , and ptd0?td7 i 15 ma maximum current for pins ptd0?td7 i ptd0?td7 25 ma maximum current into v dd i mvdd 100 ma maximum current out of v ss i mvss 100 ma storage temperature t stg 55 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 375 23.4 functional operating range 23.5 thermal characteristics characteristic symbol value unit operating temperature range t a 40 to +85 40 to +125 c operating voltage range v dd 5.0 10% 5.0 10% v characteristic symbol value unit thermal resistance qfp (64-pin) q ja 70 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c ) + p d 2 q ja w / c average junction temperature t j t a + (p d q ja ) c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 376 electrical specifications motorola 23.6 5.0-v dc electrical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?.0 ma) all i/o pins (i load = ?0.0 ma) all i/o pins (i load = ?0.0 ma) pins ptd0?td7 only maximum combined i oh for port c, port e, port f, port g, port h maximum combined i oh for port d, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ?0.8 v dd ?1.5 v dd ?0.8 50 50 100 v v v ma ma ma output low voltage (i load = 1.6 ma) all i/o pins (i load = 10 ma) all i/o pins (i load = 15 ma) pins ptd0?td7 only maximum combined i ol for port c, port e, port f, port g, port h maximum combined i ol for port d, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt 0.4 1.5 1.0 50 50 100 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd v dd v input low voltage all ports, irq , rst , osc1 v il v ss 0.3 v dd v v dd supply current run (3) wait (4) stop (5) lvi enabled, t a = 25 c lvi disabled, t a = 25 c lvi enabled, t a = ?0 c to 125 c lvi disabled, t a = ?0 c to 125 c i dd 300 20 400 50 30 12 400 50 500 100 ma ma m a m a m a m a i/o ports hi-z leakage current (6) i il ? 10 m a input current i in 1 m a pullup resistors (as input only) r pu 20 33 50 k w capacitance ports (as input or output) c out c in 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ?v low-voltage inhibit, trip falling voltage ?target v lvii 4.11 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications eeprom and memory characteristics MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 377 23.7 eeprom and memory characteristics low-voltage inhibit reset/recover hysteresis ?target h lv i 100 150 mv por rearm voltage (7) v por 0 200 mv por reset voltage (8) v porrst 0 800 mv por rise time ramp rate (9) r por 0.02 v/ms notes : 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd is measured with osc1 = v ss . 6. pullups are disabled. port b leakage is specified in 23.10 adc characteristics . 7. maximum is highest voltage that por is guaranteed. 8. maximum is highest voltage that por is possible. 9. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic symbol min max unit ram data retention voltage v rdr 0.7 v eeprom programming time per byte t eepgm 10 ms eeprom erasing time per byte t ebyte 10 ms eeprom erasing time per block t eblock 10 ms eeprom erasing time per bulk t ebulk 10 ms eeprom programming voltage discharge period t eefpv 100 m s number of programming operations to the same eeprom byte before erase (1) notes : 1. programming a byte more times than the specified maximum may affect the data integrity of that byte. the byte must be erased before it can be programmed again. 8 eeprom write/erase cycles at 10ms write time (85 c) 10,000 cycles eeprom data retention after 10,000 write/erase cycles 10 years characteristic (1) symbol min typ (2) max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 378 electrical specifications motorola 23.8 5.0-v control timing 23.9 timer interface module characteristics characteristic (1) notes : 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit frequency of operation crystal option (2) external clock option (3) 2. see 23.12 clock generation module characteristics for more information. 3. no more than 10% duty cycle deviation from 50% f osc 1 dc (4) 4. some modules may require a minimum frequency greater than dc for proper operation. see appropriate table for this information. 8.4 33.6 mhz mhz internal operating frequency f bus note (5) 5. some modules may require a minimum frequency greater than dc for proper operation. see appropriate table for this information. 8.4 mhz reset input pulse width low (6) 6. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 t cyc irq interrupt pulse width low (7) (edge-triggered) 7. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. t ilih 1.5 t cyc irq interrupt pulse period t ilil note (8) 8. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. the minimum period, t ilil or t tltl , should not be less than the number of cycles it takes to execute the interrupt service routine plus tbd t cyc . t cyc 16-bit timer input capture pulse width input capture period t th, t tl t tltl 2 note (9) 9. the minimum period, t ilil or t tltl , should not be less than the number of cycles it takes to execute the interrupt service routine plus tbd t cyc . t cyc t cyc characteristic symbol min max unit input capture pulse width t tih , t til 125 ns input clock pulse width t tch , t tcl (1/f bus )+5 ?s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications adc characteristics MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 379 23.10 adc characteristics characteristic (1) symbol min max unit comments supply voltage v ddad 4.5 (v dd min) 5.5 (v dd max) v v ddaref should be tied to the same potential as v dd via separate traces. input voltages v adin v refh 0 1.5 v ddaref v ddaref v v adin v refh resolution b ad 8 8 bits absolute accuracy (v refl = 0 v, v refh = v ddad = 5 v 10%) a ad 1/2 1 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v refl v refh v v refl = v ssa power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time (2) t ads 5 t aic cycles zero input reading (3) z adi 00 01 hex v in = v refl full-scale reading (3) f adi fe ff hex v in = v refh input capacitance c adi (20) 8 pf not tested input leakage (4) port b 1 m a notes : 1. v dd = 5.0 vdc 10%, v dda = v ddaref = 5.0 vdc 10%, v refh = 5.0 vdc 10%, v ss = 0 vdc, v refl = v ssa = 0 vdc 2. source impedances greater than 10 k w adversely affect internal rc charging time during input sampling. 3. zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 380 electrical specifications motorola 23.11 spi characteristics diagram number (1) notes : 1. numbers refer to dimensions in figure 23-1 and figure 23-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f bus(m) f bus(s) f bus /128 dc f bus /2 f bus mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 t cyc t cyc 2 enable lead time t lead(s) 15 ns 3 enable lag time t lag(s) 15 ns 4 clock (spsck) high time master slave t sckh(m) t sckh(s) 100 50 ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) 100 50 ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 20 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?5ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) 10 40 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 5 ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications spi characteristics MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 381 figure 23-1. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6? lsb in master msb out bits 6? master lsb out 11 10 11 7 6 note note: this last clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6? lsb in master msb out bits 6? master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 382 electrical specifications motorola figure 23-2. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6? 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6? msb out note: not defined but normally lsb of character previously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6? 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6? msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications clock generation module characteristics MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 383 23.12 clock generation module characteristics 23.12.1 cgm operating conditions 23.12.2 cgm component information characteristic symbol min typ max comments operating voltage v dd 4.5 v 5.5 v crystal reference frequency f rclk 1 8.4 module crystal reference frequency f xclk 4.9152 mhz same frequency as f rclk range nominal multiplier f nom 4.9152 mhz 4.5 to 5.5 v, v dd only vco center-of-range frequency (mhz) f vrs 4.9152 32.0 4.5 to 5.5 v, v dd only vco operating frequency (mhz) f vclk 4.9152 32.0 characteristic symbol min typ max unit crystal load capacitance c l consult crystal manufacturer s data crystal fixed capacitance c 1 2 c l consult crystal manufacturer s data crystal tuning capacitance c 2 2 c l consult crystal manufacturer s data feedback bias resistor r b 22m w series resistor r s 330k w 1m w not required filter capacitor multiply factor c fact 0.0154 f/s v filter capacitor c f c fact (v dda /f xclk) see 9.5.3 external filter capacitor pin (cgmxfc) . bypass capacitor c byp 0.1 m f c byp must provide low ac impedance from f = f xclk /100 to 100 f vclk , so series resistance must be considered. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 384 electrical specifications motorola 23.12.3 cgm acquisition/lock time information description (1) notes : 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ max notes manual mode time to stable t acq (8 v dda )/(f xclk k acq) if c f chosen correctly manual stable to lock time t al (4 v dda )/(f xclk k trk ) if c f chosen correctly manual acquisition time t lock t acq +t al tracking mode entry frequency tolerance d trk 0 3.6% acquisition mode entry frequency tolerance d unt 6.3% 7.2% lock entry freq. tolerance d lock 0 0.9% lock exit freq. tolerance d unl 0.9% 1.8% reference cycles per acquisition mode measurement n acq ?2 reference cycles per tracking mode measurement n trk 128 automatic mode time to stable t acq n acq /f xclk (8 v dda )/(f xclk k acq) if c f chosen correctly automatic stable to lock time t al n trk /f xclk (4 v dda )/(f xclk k trk ) if c f chosen correctly automatic lock time t lock t acq + t al pll jitter, deviation of average bus frequency over 2 ms 0 (f crys ) (.025%) (n/4) n = vco freq. mult. (gbnt) (2) 2. gbnt guaranteed but not tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications flash memory characteristics MC68HC908AB32 ? rev. 1.0 technical data motorola electrical specifications 385 23.13 flash memory characteristics characteristic symbol min max unit flash program bus clock frequency 1 mhz flash read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8.4m hz flash page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 1 ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4 ms flash pgm/erase to hven set up time t nvs 10 m s flash high-voltage hold time t nvh 5 m s flash high-voltage hold time (mass erase) t nvhl 100 m s flash program hold time t pgs 5 m s flash program time t prog 30 40 m s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1 m s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 64) t hv max. ? ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. 10,000 cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. 10,000 cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. 10 years f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical speci?ations technical data MC68HC908AB32 ? rev. 1.0 386 electrical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola mechanical specifications 387 technical data ?MC68HC908AB32 section 24. mechanical specifications 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 388 24.2 introduction this section gives the dimensions for: 64-pin plastic quad flat pack (case 840b-01) figure 24-1 shows the latest package drawing at the time of this publication. to make sure that you have the latest package specifications, contact one of the following: local motorola sales office world wide web at http://www.motorola.com/semiconductors/ follow the world wide web on-line instructions to retrieve the current mechanical specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical speci?ations technical data MC68HC908AB32 ? rev. 1.0 388 mechanical specifications motorola 24.3 64-pin plastic quad flat pack (qfp) figure 24-1. 64-pin plastic quad flat pack (qfp) l l ? ? detail a ? b a s v detail a p b b d ?? ?? ? c ? e h g m m detailc seating plane datum plane 1 16 ? 0.01 (0.004) r detail c datum plane ? t u q k w x s a? m 0.20 (0.008) d s h s a? m 0.20 (0.008) d s c 0.05 (0.002) a? s a? m 0.20 (0.008) d s c 0.05 (0.002) a? s a? m 0.20 (0.008) d s h 48 33 s a? m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h 0.25 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 0.005 u 0 ? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ??is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?? ??and ??to be determined at datum plane ?? 5. dimensions s and v to be determined at seating plane ?? 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?? 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC908AB32 ? rev. 1.0 technical data motorola ordering information 389 technical data ?MC68HC908AB32 section 25. ordering information 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.2 introduction this section contains ordering numbers for the MC68HC908AB32. 25.3 mc order numbers table 25-1. mc order numbers mc order number (1) notes : 1. fu = quad flat pack c = operating temperature range: ?0 c to +85 c m = operating temperature range: ?0 c to +125 c operating temperature range MC68HC908AB32cfu ?0 c to +85 c MC68HC908AB32mfu ?0 c to +125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data MC68HC908AB32 ? rev. 1.0 390 ordering information motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any produc t or circuit, and speci cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data s heets and/or speci cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for ea ch customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, inte nded, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or u nauthorized application, buyer shall indemnify and hold motorola and its of cers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages , and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportu nity/af rmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu, minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour center, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong . 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors/ ?motorola, inc., 2000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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